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User's Manual
PD7701x Family
Digital Signal Processor Architecture
PD77015 PD77016 PD77017 PD77018 PD77018A PD77019
Document No. U10503EJ4V0UM00 (4th edition) Date Published May 1998 N CP(K)
(c)
Printed in Japan
1993, 1994, 1995, 1998
[MEMO]
2
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after poweron for devices having reset function.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. InterTools is a trademark of TASKING, Inc.
3
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: PD77016, PD77019-013 The customer must judge the need for licence: PD77015, PD77017, PD77018, PD77018A, PD77019
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M7 96.5
4
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J98. 2
5
MAJOR REVISIONS IN THIS EDITION
Page Throughout Throughout p.30 p.41 p.62 p.67 p.69 p.96 p.97 p.116 p.166 p.175 p.183, 184 p.207 p.214 p.216 p.230 to 232 Description Addition of descriptions of PD77018A and 77019. Deletion of Chapter 5 Assembly Instructions Addition of 2.1.2 (2) 116-pin plastic BGA Addition of BGA package numbers to 2.3.2 Pin function of PD77015, 77017, 77018, 77018A, and 77019 Addition of Note 1 to Table 3-7. Initialized Pins and Their Initial Statuses Addition of Table 3-8. Pin Status in HALT Mode Addition of Table 3-9. Pin Status in STOP Mode Change of Caution in Figure 3-25. External Interrupt Timing Addition of Caution to Table 3-17. Interrupt Vector Table Change of status during reset of DA0-DA15 (13) and X/Y in Table 3-20. Pin Status Addition of description to 3.7.3 (3) (C) I/O timing of non-standard serial clock Change of descriptions of HD0-HD7 in Table 3-33. The Pin Status during and after Hardware Reset Change of 3.7.4 (5) (c) Interrupts and addition of Caution to this section Addition of 4.3.1 (2) Parameters for self-boot of PD77019-013 Addition of description of high-speed simulator (SM77016-H) to 5.1.2 Software simulator Change of part number of 5.2.2 (3) Adapter for EB-77017 board Addition of A.3 CPU Registers to Be Initialized and Initial Values to A.6 Status of Output Pins during Reset to Release STOP mode
The mark
shows major revised points.
6
PREFACE
Readers:
This manual should be read by engineers who wish to understand the functions of the PD7701x family for designing software or hardware application systems. This document describes the hardware and software functions provided in the PD7701x family products in the order shown below. This manual is designed to be used as a reference manual when developing application system hardware or software using PD7701x products.
Purpose:
Organization:
This manual consists of the following sections: * Chapter 1 ....... Overview * Chapter 2 ....... Pin Functions * Chapter 3 ....... Architecture * Chapter 4 ....... Boot Function * Chapter 5 ....... Development Tools * Appendix A .... Device Summary * Appendix B .... Ordering Information * Appendix C .... Index
How to read:
This manual assumes that readers possess basic knowledge on electric/electronic circuits, logic circuits, and microcomputers. The PD7701x family consists of the PD77016, 77015 , 77017, 77018, 77018A, and 77019. Unless otherwise specified, "PD7701x" refers to the entire family. If there are some differences in function or operation among family products, they are described under their respective names. * To understand all the PD7701x functions: Read this manual from Chapter 1 "Overview" through Chapter 4 "Boot Function" to gain a detailed understanding of the functions of this family. * If you are a hardware engineer: Read this manual from Chapter 1 "Overview" through Chapter 4 "Boot Function". You will learn various useful points for configuring a hardware system as well as gain a detailed understanding of the functions of this family. Chapter 3 "Architecture" describes the related interface levels of the on-chip function blocks. * If you are a software engineer: Read this manual from Chapter 1 "Overview" through Chapter 4 "Boot Function". You will learn various useful points for programming a software application as well as gain a detailed understanding of the functions of this family. Chapter 5 "Development Tools" introduces software development tools, additional tools for this family, and evaluation systems. Refer to "PD7701x Family User's Manual Instructions." * If you use this document as a reference manual: Note that an index is provided at the end of this manual. This index can be used to search a word based on a key word. Chapter 3 "Architecture" provides descriptions of internal device architecture on a top-down basis to facilitate searching a specific function. Appendix A "Device summary" summarizes various key points on the use of this device, such as instruction memory map, data memory map, and peripheral register map.
7
Legends:
Data weight
: Upper digit is left and lower is right.
Active low : XXX (a line is drawn over the name of pin or signal.) Memory map address : Top-Higher, Bottom-Lower Note Caution Remarks Bolded text Numerical expression : Explanation for the Note in the text. : Description that should be read carefully : Complementary explanation for the text : Important items : Binary ... 0bXXXX Decimal ... XXXX Hexadecimal ... 0xXXXX : Either of the items enclosed within { } can be selected.
{
}
8
Related Documents: Also use the following documents: [Documents related to PD7701x family] * Data sheet
Part Number Document Number
PD77016
U10891E
PD77015
PD77017
U10902E
PD77018
PD77018A
PD77019
PD77019-013
U13053E
U11849E
* User's manual and brochure
Document Name Brochure User's Manual Architecture Instructions Application Note Basic software Document Number U12395E This manual U13116E U11958E
[Documents related to development tools]
Document Name IE-77016-98/PC User's Manual IE77016-CM-EM6 User's Manual EB-77017 User's Manual Hardware Document Number EEU-1541 EEU-1506 U12660E
Some of the above related documents are preliminary versions but are not so specified here.
Caution The above related documents are subject to change without notice. Be sure to use the latest edition of the document when you design your system.
9
[MEMO]
10
CONTENTS (1/3)
Chapter 1 Overview ............................................................................................................................ 1.1 Products of PD7701x Family ............................................................................................. 1.2 Features of PD7701x Family .............................................................................................
1.2.1 1.2.2 1.2.3 Common features ....................................................................................................................... Features of PD77016 ............................................................................................................... Features of PD77015, 77017, 77018, 77018A, and 77019 ......................................................
19 20 21
21 21 21
1.3
Main Applications of PD7701x Family .............................................................................
23 25 26
26 28
Chapter 2 Pin Functions .................................................................................................................... 2.1 Pin Configurations ...............................................................................................................
2.1.1 2.1.2 Pin configuration of PD77016 .................................................................................................. Pin configuration of PD77015, 77017, 77018, 77018A, and 77019 ......................................... Pin organization of PD77016 ................................................................................................... Pin organization of PD77015, 77017, 77018, 77018A, and 77019 .......................................... Comparison in pin configurations of PD7701x family ............................................................... Pin function of PD77016 .......................................................................................................... Pin function of PD77015, 77017, 77018, 77018A, and 77019 .................................................
2.2
Pin Organizations ................................................................................................................
2.2.1 2.2.2 2.2.3
32
32 33 34
2.3
Pin Functions .......................................................................................................................
2.3.1 2.3.2
35
35 41
2.4
Handling of Unused Pins ....................................................................................................
47 49 49 51
51 53
Chapter 3 Architecture ...................................................................................................................... 3.1 Overall Block Organization ................................................................................................. 3.2 Buses ....................................................................................................................................
3.2.1 3.2.2 Main bus ..................................................................................................................................... Data bus ..................................................................................................................................... Clock generator .......................................................................................................................... Reset function ............................................................................................................................ Pipeline architecture ................................................................................................................... Standby function ........................................................................................................................ Block configuration ..................................................................................................................... Program execution control block ................................................................................................ Flow control block ....................................................................................................................... Interrupt ...................................................................................................................................... Error status register (ESR) ......................................................................................................... Block configuration ..................................................................................................................... Data memory space ................................................................................................................... Addressing mode ....................................................................................................................... Block configuration ..................................................................................................................... General-purpose registers and data formats ............................................................................. Operation functions of multiply accumulator (MAC) and MAC input shifter (MSFT) .................. Operation functions of arithmetic and logic unit (ALU) ...............................................................
3.3
System Control Units ..........................................................................................................
3.3.1 3.3.2 3.3.3 3.3.4
57
57 61 63 66
3.4
Program Control Unit ..........................................................................................................
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5
71
71 72 86 94 110 111 112 124 136 136 141 147
3.5
Data Addressing Unit .......................................................................................................... 111
3.5.1 3.5.2 3.5.3
3.6
Operation Unit ...................................................................................................................... 135
3.6.1 3.6.2 3.6.3 3.6.4
11
CONTENTS (2/3)
3.6.5
Operation functions of barrel shifter (BSFT) ............................................................................... Block configuration ..................................................................................................................... Peripheral registers .................................................................................................................... Serial interface ........................................................................................................................... Host interface ............................................................................................................................. General-purpose input/output port ............................................................................................. Wait controller ............................................................................................................................ Debug interface (JTAG) ..............................................................................................................
149 151 152 153 171 185 194 195
3.7
Peripheral Units ................................................................................................................... 151
3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7
Chapter 4 Boot Function ................................................................................................................... 199 4.1 General .................................................................................................................................. 200 4.2 Boot Modes .......................................................................................................................... 201
4.2.1 Classification of boot modes ...................................................................................................... Self-boot operation ..................................................................................................................... Host boot operation .................................................................................................................... Parameters of X memory word or byte reboot ........................................................................... Parameters of Y memory word or byte reboot ........................................................................... Parameters for host reboot ......................................................................................................... 201 205 208 210 211 211
4.3
Boot at Reset ........................................................................................................................ 205
4.3.1 4.3.2
4.4
Boot Subroutine (reboot) .................................................................................................... 210
4.4.1 4.4.2 4.4.3
4.5
Boot Time ............................................................................................................................. 212
Chapter 5 Development Tools .......................................................................................................... 213 5.1 Software Tools ....................................................................................................................... 213
5.1.1 5.1.2 5.1.3 5.1.4 Integrated development environment work bench (WB77016) .................................................. Software simulator (SM77016, SM77016-H) .............................................................................. C compiler (InterToolsTM 77016) ................................................................................................. System software for in-circuit emulator (ID77016) ..................................................................... In-circuit emulator ....................................................................................................................... Options for in-circuit emulators ................................................................................................... 214 214 214 214 215 215
5.2
Hardware Tools .................................................................................................................... 215
5.2.1 5.2.2
Appendix A Device Summary .......................................................................................................... 217 A.1 Register List ......................................................................................................................... 217
A.1.1 A.1.2 CPU registers ............................................................................................................................. Peripheral registers .................................................................................................................... 217 221
A.2 A.3 A.4 A.5 A.6 A.7
Interrupt Vector Table .......................................................................................................... CPU Registers to Be Initialized and Initial Values ............................................................ Memory-Mapped Registers to Be Initialized and Initial Values ....................................... Pins to Be Initialized and Initial Status .............................................................................. Status of Output Pins during Reset to Release STOP Mode ........................................... Memory Map .........................................................................................................................
A.7.1 A.7.2 Instruction memory map ............................................................................................................. Data memory map (X/Y) .............................................................................................................
230 230 231 231 232 233
233 233
12
CONTENTS (3/3)
Appendix B Ordering Information ................................................................................................... 235 B.1 Ordering Information ........................................................................................................... 235 B.2 Mask Option ......................................................................................................................... 236
B.2.1 B.2.2 Disabling CLKOUT output .......................................................................................................... Clock multiple ............................................................................................................................. 236 236
B.3 Mask ROM Ordering Format ............................................................................................... 236 Appendix C Index ............................................................................................................................... 237 C.1 Key Words ............................................................................................................................ 237 C.2 Acronyms, etc. ..................................................................................................................... 242
13
LIST OF FIGURES (1/3)
Figure No. 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 3-6 3-7
Title 160-pin Plastic QFP ......................................................................................................................... 100-pin Plastic TQFP ....................................................................................................................... 116-Pin Plastic BGA ......................................................................................................................... Pin Organization of PD77016 ........................................................................................................ Pin Organization of PD77015, 77017, 77018, 77018A, and 77019 ............................................... Comparison in Pin Configurations of PD7701x Family .................................................................. Overall Block Organization ............................................................................................................... Clock Circuit of PD77016 ............................................................................................................... Clock Timing of PD77016 .............................................................................................................. Clock Circuit of PD77015, 77017, 77018, 77018A, 77019 ............................................................ Clock Timing of PD77015, 77017, 77018, 77018A, 77019 ............................................................ Reset Timing .................................................................................................................................... Pipeline Image ................................................................................................................................. (a) Pipeline image 1 ........................................................................................................................ (b) Pipeline image 2 ........................................................................................................................
Page 26 28 30 32 33 34 50 57 58 59 60 63 64 64 64 67 67 68 68 71 72 75 75 75 76 78 79 80 83 83 84 84 88 90 90 91 93 96
3-8
HALT Mode ...................................................................................................................................... (a) Releasing from HALT mode (by using interrupt) ........................................................................ (b) Timing of setting HALT mode ..................................................................................................... (c) Timing of releasing HALT mode .................................................................................................
3-9 3-10 3-11
Program Control Unit ....................................................................................................................... Instruction Memory Space ............................................................................................................... Instruction Memory Operation Timing .............................................................................................. (a) Read operation timing ................................................................................................................ (b) Write operation timing ................................................................................................................
3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28
Instruction Memory Control Banks and IWTR Field Configuration ................................................... Valid Timing of Instruction Memory Wait Control .............................................................................. Example of External Instruction Memory Interface .......................................................................... Normal Operation of PC ................................................................................................................... Timing of Unconditional Immediate Jump ........................................................................................ Timing of Unconditional Indirect Jump ............................................................................................. Timing of Conditional Immediate Jump (condition satisfied: branch) ............................................... Timing of Conditional Immediate Jump (condition not satisfied: pass) ............................................ Format of RC .................................................................................................................................... Example of Repeat Instruction (repetition of 2 times) ...................................................................... Repeat Execution Timing (repetition of 2 times) .............................................................................. Format of LC .................................................................................................................................... Loop Execution Timing (example of 2 loops operation) ................................................................... External Interrupt Timing ..................................................................................................................
Multiple Interrupt Processings .......................................................................................................... 103 Interrupt Acknowledging Timing ....................................................................................................... 105 Timing by RETI Instruction ............................................................................................................... 106 (a) Unconditional ............................................................................................................................. 106 (b) Conditional instruction: Condition satisfied ................................................................................ 106
3-29
Interrupt Delay Timing (one-cycle delay) .......................................................................................... 107
14
LIST OF FIGURES (2/3)
Figure No. 3-30 3-31 3-32 3-33
Title
Page
Interrupt Delay Timing (two-cycle delay) .......................................................................................... 108 Data Addressing Unit ....................................................................................................................... 111 X/Y Data Memory Map ..................................................................................................................... 112 Timing of Data Memory Read Cycle ................................................................................................ 117 (a) Without wait cycles .................................................................................................................... 117 (b) With wait cycles ......................................................................................................................... 117
3-34
Timing of Data Memory Write Cycle ................................................................................................. 118 (a) Without wait cycles .................................................................................................................... 118 (b) With wait cycles ......................................................................................................................... 118
3-35
Data Memory Control Bank and DWTR Field Configuration ............................................................ 120 (a) PD77016 .................................................................................................................................. 120 (b) PD77015, 77017, 77018, 77018A, 77019 ............................................................................... 120
3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54
Bus Arbitration Procedure ................................................................................................................ 122 Reversing Bits of DPn ...................................................................................................................... 128 Division of DPn ................................................................................................................................. 130 Mapping of Ordinary Modulo Operation ........................................................................................... 131 Mapping of Modulo Adjustment ........................................................................................................ 131 Operation Unit .................................................................................................................................. 136 Formats of General-purpose Registers ............................................................................................ 137 Data Exchange between General-purpose Registers and Data Memory ........................................ 138 Signed-Signed Multiply .................................................................................................................... 142 Signed-Unsigned Multiply ................................................................................................................ 142 Unsigned-Unsigned Multiply ............................................................................................................ 143 Accumulative Multiplication .............................................................................................................. 145 1-Bit Shift Accumulative Multiplication .............................................................................................. 145 16-Bit Shift Accumulative Multiplication ............................................................................................ 146 Barrel Shifter Operations .................................................................................................................. 150 Peripheral Units ................................................................................................................................ 151 Serial Interface ................................................................................................................................. 153 Function Diagram of Serial Interface (1 channel) ............................................................................. 156 Serial Interface Output timing ........................................................................................................... 163 (a) Continuous data ......................................................................................................................... 163 (b) Non-continuous data .................................................................................................................. 163
3-55
Serial Interface Input timing ............................................................................................................. 165 (a) SICM = 1, SIEF = 0; Continuous mode ..................................................................................... 165 (b) SICM = 0, SIEF = 1; Single mode ............................................................................................. 165
3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63
Serial Interfaces - Operation of the Serial Clock Counter ................................................................ 166 Host Interface ................................................................................................................................... 171 Function Diagram of Host Interface ................................................................................................. 173 Host Read Sequence (PD7701x --> host): HDT read without wait .............................................. 179 Host Write Sequence (PD7701x <-- host): HDT write without wait .............................................. 180 General-purpose Input/Output Port .................................................................................................. 185 Wait Controller ................................................................................................................................. 194 Appearance of JTAG Pins ................................................................................................................ 197
15
LIST OF FIGURES (3/3)
Figure No. 3-64
Title
Page
The JTAG Pin Processing ................................................................................................................ 197 (a) PD77016 .................................................................................................................................. 197 (b) PD77015, 77017, 77018, 77018A, 77019 ............................................................................... 198
4-1
Example of Self-boot System Configuration .................................................................................... 202 (a) PD77016 .................................................................................................................................. 202 (b) PD77015, 77017, 77018, 77018A, 77019 ............................................................................... 202
4-2
Configuration Example of Host Boot System ................................................................................... 203 (a) PD77016 .................................................................................................................................. 203 (b) PD77015, 77017, 77018, 77018A, 77019 ............................................................................... 203
4-3 4-4 4-5
Illustration of Word Boot ................................................................................................................... 204 Illustration of Byte Boot .................................................................................................................... 204 Host Boot Procedure ........................................................................................................................ 208
16
LIST OF TABLES (1/2)
Table No. 1-1 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23
Title Features of PD7701x Family ......................................................................................................... Handling of Unused Pins ................................................................................................................. Registers Connected to Main Bus ................................................................................................... Functional Block and Bus ................................................................................................................ Registers and Memories Connected to X Data Bus ......................................................................... Registers and Memories Connected to Y Data Bus ......................................................................... CPU Registers to Be Initialized and Their Initial Values ................................................................... Initialized Memory-mapped Registers and Their Initial Values ........................................................ Initialized Pins and Their Initial Statuses .......................................................................................... Pin Status in HALT Mode ................................................................................................................. Pin Status in STOP Mode ................................................................................................................ Output Pin Status during Reset Period after Releasing STOP Mode .............................................. Capacity of Internal Instruction Memory ........................................................................................... Capacity of External Memory ........................................................................................................... Pin Statuses ..................................................................................................................................... Set Values of IWTR Fields and Number of Wait Cycles ................................................................... Classification of Branch Instructions ................................................................................................ Interrupt Causes ............................................................................................................................... Interrupt Vector Table .......................................................................................................................
Page 22 47 52 53 54 55 61 62 62 67 69 70 73 73 74 77 82 94 97
ROM and RAM Capacities ............................................................................................................... 113 Capacity of External Data Memory .................................................................................................. 114 Pin Status ......................................................................................................................................... 116 Set Value of DWTR Field and Number of Wait Cycles ..................................................................... 121 Simultaneous Access to X and Y Memory Spaces .......................................................................... 123 Modifying Data Pointers ................................................................................................................... 129 (a) Operation ................................................................................................................................... 129 (b) Value range ................................................................................................................................ 130
3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38
Formats of General-purpose Registers ............................................................................................ 137 Accumulative Multiplication Function ............................................................................................... 144 Memory Mapping of Peripheral Registers ........................................................................................ 152 Status Indicators of Serial Input/output Interfaces ........................................................................... 155 Pins Status during and after Hardware Reset .................................................................................. 157 Conditions of Serial Input/output Error Flags Settings ..................................................................... 159 Functions of SST (SST1:0x3801:X/:Y, SST2:0x3803:X/:Y) ............................................................. 160 Combination of SICM and SIEF Bits ................................................................................................ 161 Status Indicators of Host Read/write Interface ................................................................................. 173 The Pins Status during and after Hardware Reset ........................................................................... 175 Function of HST (0x3807:X/:Y) ........................................................................................................ 177 Conditions of Host Input/Output Error Flags Settings ...................................................................... 178 Selecting Host Interface Registers ................................................................................................... 178 Port Command Register (PCD - 0x3805:X/:Y) ................................................................................. 188 Test Instructions ............................................................................................................................... 196
17
LIST OF TABLES (2/2)
Table No. 4-1 4-2 4-3 4-4 4-5 4-6
Title
Page
P0 and P1 Reset Values and Boot Modes ....................................................................................... 205 Parameters for Self-booting (0x4000: Y) .......................................................................................... 206 Memory Map of Parameters for Word Boot ..................................................................................... 206 Memory Map of Parameters for Byte Boot ....................................................................................... 207 Boot Subroutine Entry Points ........................................................................................................... 210 Boot Time ......................................................................................................................................... 212
18
Chapter 1
Overview
As the 21st century approaches, multi-media systems that do not only compute numeric data and process information as conventional computer systems do, but can also process images and sounds, which are important interfacing elements for human beings, have come in the limelight. Another important feature of multi-media systems is that they must provide a real-time processing capability. As a result, the quantity of information that must be communicated and processed is substantially increasing, the current architecture which heavily depends on the CPU for processing information, must be reviewed, and data processing systems that facilitate organizing multi-media systems are being increasingly demanded. The PD7701x family is a collection of 16-bit fixed-point digital signal processors (DSPs) of the new generation that have been developed for digital signal processing applications, including multi-media systems, which require high speed and high accuracy. Their internal circuit consists of eight 40-bit general-purpose registers that are used to load/ store or input/output data, a multiply accumulator that performs an operation of "16 bits x 16 bits + 40 bits --> 40 bits", a 40-bit ALU, and a 40-bit barrel shifter. By employing as the basic technology the Harvard architecture, in which the instruction memory space and the data memory space are separated, and by separating the data memory space into X and Y memory areas, the PD7701x family can execute flexible, high-speed data transfer. These DSPs are provided with two serial interfaces, a host interface, and general-purpose I/O ports as peripherals. Because these interface registers are mapped on the data memory space, various peripheral control operations can be performed by all addressing modes provided for the data memory. The basic operation of the PD7701x family is executed by using a pipeline of three stages: instruction fetch, instruction decode, and instruction execution. Some instructions, however, do not use this pipeline, but are designed so that their execution results can be used by the next instruction. Therefore, you can program your applications without having to pay any special attention to the pipeline.
1 2 3 4 5 6 A B C
PD7701x Family User's Manual
19
Chapter 1 Overview
1.1 Products of PD7701x Family
1.1
Products of PD7701x Family
The PD7701x family consists of the following products: * PD77016 * PD77015 * PD77017 * PD77018 * PD77018A * PD77019
20
PD7701x Family User's Manual
Chapter 1 Overview
1.2 Features of PD7701x Family
1.2
Features of PD7701x Family
The PD7701x family is provided with sophisticated next-generation DSP functions in addition to standard DSP technological features. The features common to all the models in the PD7701x family and the features of each model are described below. Table 1-1 shows the differences among the PD7701x family products.
1.2.1 Common features
* High-speed instruction cycle: 30 ns (PD77016, 77015, 77017, 77018) 16.6 ns (PD77018A, 77019) * Harvard architecture eliminating bus neck * Three stage pipeline architecture * Rational combination of parallel instructions * Multiply accumulator capable of executing 3-operand instructions (trinomial operation) * Eight 40-bit general-purpose registers * Eight data memory pointer registers (four each for X and Y memories) * Dual data memory space promising flexible, high-speed data transfer * Many addressing mode enabling flexible memory access * Head room format eliminating operational overflow * Various internal peripheral interfaces * Many external interfaces * Interrupt functions covering wide range of applications (internal: 6 levels, external: 4 levels) * Hardware loop mechanism minimizing overhead * Programmable external memory access wait * Boot ROM * Debug function (JTAG port) * Standby function by HALT instruction
1.2.2 Features of PD77016
The PD77016 is the basic model of the PD7701x family. Because it supports an external memory area of sufficient capacity for both instructions and data in addition to the common features of the PD7701x family, the PD77016 can cover a wide range of applications.
1.2.3 Features of PD77015, 77017, 77018, 77018A, and 77019
The PD77015, 77017, 77018, 77018A, and 77019 are ideally suited for compact and economical embedded systems, being provided with a clock multiplier circuit (mask option), a crystal oscillator circuit, a single, 3-V power supply, a power down function, and a 100-pin TQFP package in addition to the common features of the PD7701x family. The only difference among these models is the capacity of the internal ROM and RAM. Select the model best suited to your application. The PD77019-013 invalidates the internal ROM of the PD77019. Because mask processing is not necessary, use this model when only the internal RAM is used.
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Chapter 1 Overview
1.2 Features of PD7701x Family
Table 1-1. Features of PD7701x Family
Items
PD77016
Instruction cycle Clock rate (@ max. rate)
PD7701x family PD77015 PD77017 PD77018 PD77018A PD77019
30 ns(@ max. clock rate) Ext. 66 MHz Ext. 33 MHz (x1 mask option) Ext. 16.5 MHz (x2 mask option) Ext. 8.25 MHz (x4 mask option) Ext. 4.125 MHz (x8 mask option) Ext. 33 MHz crystal (x1 mask option)
16.6 ns (@ max. clock rate) Ext. 60 MHz (x1 mask option), Ext. 30 MHz (x2 mask option), Ext. 20 MHz (x3 mask option), Ext. 15 MHz (x4 mask option), Ext. 7.5 MHz (x8 mask option) Ext. 60 MHz crystal (x1 mask option)
Parallel instruction execution
Trinomial operation & parallel load/store Binomial operation & parallel load/store Monomial operation & Conditional Register-to-register transfer & Conditional Branch & Conditional
Hardware loop Conditional instruction Multiply accumulator
Nesting of up to 4 levels Conditional operation, conditional transfer, conditional branch by combining standard conditional instructions with other instructions 16 bits x 16 bits + 40 bits --> 40 bits (such as trinomial operation: R0 = R0 + R1H * R2L) 40-bit inputs and 40-bit output (binomial and monomial) Eight 40-bits registers (R0-R7) Four pointers for X memory (DP0-DP3), Four pointers for Y memory (DP4-DP7) Internal: 6 levels (6 causes), External: 4 levels (4 causes) Instruction fetch, instruction decode, instruction execution 256 words (for boot function) n/a 1.5 K words 48 K words n/a 2 K words 48 K words n/a 2 K words 48 K words 2 channels 8-bit parallel Four ports (signal direction specifiable independently) +5 V 10 % +2.7 to +3.6 V 4 K words 256 words n/a 2 K words 1 K words 16 K words 2 K words 1 K words 16 K words 12 K words 256 words n/a 4 K words 2 K words 16 K words 4 K words 2 K words 16 K words 24 K words 256 words n/a 12 K words 3 K words 16 K words 12 K words 3 K words 16 K words 24 K words 256 words n/a 12 K words 3 K words 16 K words 12 K words 3 K words 16 K words 24 K words 4K words n/a 12 K words 3 K words 16 K words 12 K words 3 K words 16 K words
Accumulator General register Data memory pointer Interrupt 3-stage pipeline processing Instruction memory (32 bits/word) Boot ROM Int. ROM Int. RAM Ext. area X data memory (16 bits/word) Int. ROM Int. RAM Ext. area Y data memory (16 bits/word) Int. ROM Int. RAM Ext. area Serial interface Host interface I/O port Supply voltage Standby function Powerdown function Package
2 channels (without SORQ2, SIAK2 signals)
Entered when HALT instruction is executed. n/a Entered when STOP instruction is executed 100-pin plastic TQFP, 116-pin plastic BGA 100-pin plastic TQFP
160-pin plastic 100-pin plastic TQFP QFP Debugging function (JTAG port) CMOS technology
Miscellaneous
Remark
n/a: not available
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PD7701x Family User's Manual
Chapter 1 Overview
1.3 Main Applications of PD7701x Family
1.3
Main Applications of PD7701x Family
As its name implies, a DSP is a device developed for digital signal processing. DSPs employing next generation technology, such as the PD7701x family, are also provided with the functions of a general-purpose CPU, including a memory access capability and interrupt functions. Therefore, the PD7701x can cover a wide range of applications. The main applications of these DSPs are listed below, by field.
General signal processing
* Digital filter (FIR filter, BIQUAD filter, etc.) * High-speed Fourier transformation * Hilbert transformation * Relative processing * Adaptive filter
Communication field
* High-speed modem (V.32, etc.) * Digital cellular telephone (voice codec, equalizer, etc.) * MPEG * Echo canceler * Adaptive equalizer * Digital PBX * DTMF encoder/decoder * FAX * Spread spectrum communication * Multiplexed communication
Sound/acoustic
* Voice recognition * Sound coding/decoding (ADPCM, PARCOR, etc.) * Speech synthesis (phoneme synthesis, rule synthesis, etc.) * Synthesizer * Electronic musical instrument * Sound field control * Sound effects
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Chapter 1 Overview
1.3 Main Applications of PD7701x Family
Image processing/graphics
* Affine transformation * 2-dimension orthogonal transformation (Fourier transformation, Hadamard transformation, KL transformation, etc.) * Filtering (smoothing, median filter, etc.) * Various operators (Laplacian, Sobel, etc.) * Ray tracing, Mandelbrot * CAD (3D graphics, etc.) * Virtual reality * Image compression/expansion (DCT, run length, variable-length coding) * Image recognition * Computer animation
Control
* Navigation system * Disc control (CD, LD, etc.) * Various servo systems (PID, AC servo, etc.) * Control of laser printer and copier * Robot * NC control * Fuzzy control
Measurement
* Spectrum analyzer * Function generator * Pattern matching * Lock-in amplifier * Box car integrator * Various analysis systems (vibration analysis, transient analysis)
General numeric processing and others
* Data enciphering/deciphering * Use as numerical processor * Neural system
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PD7701x Family User's Manual
Chapter 2
Pin Functions
This chapter describes the pin configurations and pin functions of the PD7701x family. The following are the pin names:
1 2 3 4 5 6 A B C
BSTB CLKIN CLKOUT D0-D15 DA0-DA15 GND HA0, HA1 HCS HD0-HD7 HOLDAK HOLDRQ HRD HRE HWE HWR IA0-IA15 I.C. ID0-ID31 INT1-INT4 MRD
: Bus Strobe : Clock Input : Clock Output : 16-bit Data Bus : External Data Memory Address Bus : Ground : Host Data Access : Host Chip Select : Host Data Bus : Hold Acknowledge : Hold Request : Host Read : Host Read Enable : Host Write Enable : Host Write : External Instruction Memory Address Bus : Internally Connected : External Instruction Memory Data Bus : Interrupt : Memory Read Output
MWR NC P0-P3 PWR RESET SCK1, SCK2 SI1, SI2 SIAK1, SIAK2 SIEN1, SIEN2 SO1, SO2 SOEN1, SOEN2
: Memory Write Output : Non-connection : Port : Program Memory Write Strobe : Reset : Serial Clock Input : Serial Data Input : Serial Input Acknowledge : Serial Input Enable : Serial Data Output : Serial Output Enable
SORQ1, SORQ2 : Serial Output Request TCK TDI TDO TICE TMS VDD WAIT X/Y X1, X2 : Test Clock : Test Data Input : Test Data Output : Test for In-circuit Emulator : Test Mode Select : Power Supply : Wait Input : X / Y Memory Select : Crystal Connection
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Chapter 2 Pin Functions
2.1 Pin Configurations
2.1
Pin Configurations
2.1.1 Pin configuration of PD77016
* PD77016GM-KMD: 160-pin plastic QFP (fine pitch) (24 x 24 mm)
Figure 2-1. 160-pin Plastic QFP
RESET INT4 INT3 INT2 INT1 WAIT HOLDRQ CLKIN P3 P2 P1 P0 CLKOUT GND VDD MWR MRD BSTB HOLDAK X/Y DA15 DA14 DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 1 120 2 119 3 118 4 117 5 116 6 115 7 114 8 113 9 112 10 111 11 110 12 109 13 108 14 107 15 106 16 105 17 104 18 103 19 102 20 101 21 100 22 99 23 98 24 97 25 96 26 95 27 94 28 93 92 29 91 30 90 31 89 32 88 33 87 34 86 35 85 36 84 37 83 38 82 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
NC ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 VDD GND ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15 VDD GND ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23 VDD GND PWR ID24 ID25 ID26 ID27 ID28 ID29 ID30 ID31
IA0 IA1 IA2 IA3 VDD GND IA4 IA5 IA6 IA7 IA8 IA9 IA10 IA11 VDD GND IA12 IA13 IA14 IA15 TMS TDI TCK TICE TDO VDD GND HWE HRE HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA1 HA0 HWR
26
D15 D14 D13 D12 GND VDD D11 D10 D9 D8 D7 D6 D5 D4 GND VDD D3 D2 D1 D0 GND VDD SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 GND VDD SOEN2 SORQ2 SO2 SIAK2 SCK2 SIEN2 SI2 HCS HRD
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Chapter 2 Pin Functions
2.1 Pin Configurations
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin name RESET INT4 INT3 INT2 INT1 WAIT HOLDRQ CLKIN P3 P2 P1 P0 CLKOUT GND VDD MWR MRD BSTB HOLDAK X/Y DA15 DA14 DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0
Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pin name D15 D14 D13 D12 GND VDD D11 D10 D9 D8 D7 D6 D5 D4 GND VDD D3 D2 D1 D0 GND VDD SI1 SIEN1 SCK1 SIAK1 SO1 SORQ1 SOEN1 GND VDD SOEN2 SORQ2 SO2 SIAK2 SCK2 SIEN2 SI2 HCS HRD
Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin name HWR HA0 HA1 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HRE HWE GND VDD TDO TICE TCK TDI TMS IA15 IA14 IA13 IA12 GND VDD IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 GND VDD IA3 IA2 IA1 IA0
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Pin name ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 PWR GND VDD ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 GND VDD ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 GND VDD ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 NC
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Chapter 2 Pin Functions
2.1 Pin Configurations
2.1.2 Pin configuration of PD77015, 77017, 77018, 77018A, and 77019
(1) 100-pin plastic TQFP (FINE PITCH) (14 x 14 mm)
* * * * *
PD77015GC-xxx-9EU PD77017GC-xxx-9EU PD77018GC-xxx-9EU PD77018AGC-xxx-9EU PD77019GC-xxx-9EU
Figure 2-2. 100-pin Plastic TQFP
RESET INT4 INT3 INT2 INT1 I.C. X/Y DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 58 18 57 19 56 20 55 21 54 22 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
WAIT BSTB MRD VDD GND MWR HOLDAK HOLDRQ TMS TDI TCK TICE TDO CLKOUT VDD X1 X2 GND HA1 HA0 HWR HRD HCS HD0 HD1
HD2 HD3 HD4 HD5 HD6 HD7 VDD GND HWE HRE P0 P1 P2 P3 SI2 SIEN2 SCK2 SO2 SOEN2 VDD GND SOEN1 SORQ1 SO1 SIAK1
28
D15 D14 D13 D12 GND VDD D11 D10 D9 D8 GND VDD D7 D6 D5 D4 GND VDD D3 D2 D1 D0 SI1 SIEN1 SCK1
PD7701x Family User's Manual
Chapter 2 Pin Functions
2.1 Pin Configurations
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Pin name RESET INT4 INT3 INT2 INT1 I.C.
Note
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pin name D15 D14 D13 D12 GND VDD D11 D10 D9 D8 GND VDD D7 D6 D5 D4 GND VDD D3 D2 D1 D0 SI1 SIEN1 SCK1
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Pin name SIAK1 SO1 SORQ1 SOEN1 GND VDD SOEN2 SO2 SCK2 SIEN2 SI2 P3 P2 P1 P0 HRE HWE GND VDD HD7 HD6 HD5 HD4 HD3 HD2
Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pin name HD1 HD0 HCS HRD HWR HA0 HA1 GND X2 X1 VDD CLKOUT TDO TICE TCK TDI TMS HOLDRQ HOLDAK MWR GND VDD MRD BSTB WAIT
X/Y DA13 DA12 GND VDD DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 GND VDD DA3 DA2 DA1 DA0
Note Leave this pin unconnected because the I.C. pin is connected to internal circuits.
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Chapter 2 Pin Functions
2.1 Pin Configurations
(2) 116-pin plastic BGA (FINE PITCH) (12 x 12 mm)
* PD77018AS9-xxx-YJC
Figure 2-3. 116-Pin Plastic BGA
(Bottom View) 13 12 11 10 9 8 7 6 5 4 3 2 1 NML K J HGF EDCBA
(Top View)
ABCDE FGH J K LMN Index mark
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PD7701x Family User's Manual
Chapter 2 Pin Functions
2.1 Pin Configurations
Pin No. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5
Pin name BSTB VDD MWR HOLDAK TDI TDO VDD HA1 HRD HCS HD0 WAIT VDD VDD GND HOLDRQ TCK CLKOUT X2 HA0 VDD HD1 HD2 HD3 RESET VDD VDD MRD GND
Pin No. C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3
Pin name TMS TICE X1 GND HWR VDD VDD HD5 INT2 INT4 INT3 HD4 VDD VDD X/Y INT1 I.C.Note HD6 HD7 HWE VDD DA13 DA12 GND P0 HRE DA10 GND DA11
Pin No. G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8
Pin name P1 P3 P2 DA7 DA9 DA8 SI2 SCK2 SIEN2 DA4 DA6 DA5 SO2 SOEN2 VDD VDD VDD GND GND GND SOEN1 DA3 VDD D14 GND D10 GND D6 GND
Pin No. L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12
Pin name D2 D0 GND SIAK1 SORQ1 DA2 DA1 DA0 GND D11 D9 D7 D5 D3 GND GND SCK1 SO1 D15 D13 D12 VDD D8 VDD D4 VDD D1 SI1 SIEN1
Note Leave this pin unconnected because the I.C. pin is connected to internal circuits.
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Chapter 2 Pin Functions
2.2 Pin Organizations
2.2
Pin Organizations
This section describes the pin connections shown in section 2.1 by function.
2.2.1 Pin organization of PD77016
The figure below shows the pin organization of the PD77016.
Figure 2-4. Pin Organization of PD77016
+5 V
Serial interface #1
Serial interface #2
Port
(4)
(2)
Host interface
(8)
Debug interface
(2) (3)
SO1 VDD RESET INT1 SORQ1 INT2 SOEN1 INT3 SCK1 INT4 SI1 SIEN1 CLKIN SIAK1 CLKOUT SO2 SORQ2 PWR SOEN2 IA0-IA15 SCK2 ID0-ID31 SI2 SIEN2 HOLDRQ SIAK2 BSTB P0-P3 HOLDAK HCS HA0, HA1 HRD X/Y HRE DA0-DA15 HWR D0-D15 HWE WAIT HD0-HD7 MRD TDO, TICE MWR TCK, TDI, TMS GND
Reset, Interrupt
Clock External instruction memory
(16) (32)
Data bus control
(16) (16)
External data memory
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Chapter 2 Pin Functions
2.2 Pin Organizations
2.2.2 Pin organization of PD77015, 77017, 77018, 77018A, and 77019
The figure below shows the pin organization of the PD77015, 77017, 77018, 77018A, and 77019.
Figure 2-5. Pin Organization of PD77015, 77017, 77018, 77018A, and 77019
+3 V
Serial interface #1
Serial interface #2
SO1 SORQ1 SOEN1 SCK1 SI1 SIEN1 SIAK1 SO2 SOEN2 SCK2 SI2 SIEN2 P0-P3
VDD
RESET INT1 INT2 INT3 INT4 X1 X2 CLKOUT
Reset, Interrupt
Clock
Port
(4)
HOLDRQ BSTB HOLDAK
Data bus control
(2)
Host interface
(8)
Debug interface
(2) (3)
HCS HA0, HA1 HRD HRE HWR HWE HD0-HD7 TDO, TICE TCK, TDI, TMS GND
X/Y DA0-DA13 D0-D15 WAIT MRD MWR
(14) (16)
External data memory
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Chapter 2 Pin Functions
2.2 Pin Organizations
2.2.3 Comparison in pin configurations of PD7701x family
Some pins of the PD77016 are different in configuration from those of the PD77015, 77017, 77018, 77018A, and 77019 as shown in the comparative figure below.
Figure 2-6. Comparison in Pin Configurations of PD7701x Family
PD77015, 77017, 77018, 77018A, 77019
+3 V +5 V VDD SO1 SORQ1 Serial interface #1 SOEN1 SCK1 SI1 SIEN1 SIAK1 SO2
PD77016
GND RESET INT1 INT2 INT3 INT4 Reset, Interrupt
CLKIN
CLKOUT
X1 X2
Clock
SORQ2
Serial interface #2 SOEN2 SCK2 SI2 SIEN2
PWR IA0-IA15 ID0-ID31
HOLDRQ
16 32
Instruction memory interface
SIAK2
Port
4 4
P0-P3 HCS
BSTB HOLDAK
Data bus control
2
2
HA0, HA1 HRD HRE HWR HWE
X/Y
Host interface
DA0-DA15
D0-D15 WAIT MRD MWR
16 16
DA0-DA13
14 16
Data memory interface
8
8
HD0-HD7 TDO TICE
Debug interface
TCK TDI TMS
Remark
Italicized pins are those which separate the PD77016 from the other family members.
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Chapter 2 Pin Functions
2.3 Pin Functions
2.3
Pin Functions
2.3.1 Pin function of PD77016
(1) Power supply
Pin name VDD Pin No. 15, 26, 36, 46, 56, 62, 71, 95, 106, 116, 131, 141, 151 14, 25, 35, 45, 55, 61, 70, 94, 105, 115, 130, 140, 150 I/O -- Function +5-V power supply. Connect all these pins to a +5-V power supply.
GND
--
Ground. Connect all these pins to 0 V.
(2) System control
Pin name CLKIN Pin No. 8 I/O Input Function Clock input. Always supply the clock in normal device operation. In the standby mode, however, clock supply may be stopped. Internal system clock output. Clock divided by two in synchronization with CLKIN. Used for processing by an external circuit in synchronization with the instruction cycle of the PD77016. Internal system reset signal input. Initializes the hardware of the device. Be sure to input the RESET signal after power application to the device.
CLKOUT
13
Output
RESET
1
Input
(3) Interrupt
Pin name INT1-INT4 Pin No. 5-2 I/O Input Function External interrupt inputs. These interrupt inputs can be masked and are detected at the falling edge. If interrupts conflict, a one level recording function is available for each input.
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Chapter 2 Pin Functions
2.3 Pin Functions
(4) External data memory interface
Pin name X/Y Pin No. 20 I/O Output (3S) Function Memory space select signal output. * 0: Selects X memory space. * 1: Selects Y memory space. The X and Y memory spaces of an external memory cannot be accessed at the same time. Address bus for external data memory. * Accesses an external memory. When external memory is not accessed, this bus keeps outputting the address of the external memory memory location accessed last. If the external has never been accessed after reset, it outputs a low level (0x0000). 16-bit data bus. * Accesses an external memory. Read output. * External memory read. Write output. * External memory write. Wait signal input. Wait cycles specified by DWTR (data memory wait cycle register) are inserted when the external data memory is accessed, and this signal is sampled at the end of the wait cycles. While the WAIT signal is active (low level), wait cycles are unconditionally inserted. * 0: Wait * 1: No wait (If the wait cycle specified by DWTR has been completed.) Hold request signal input. An external circuit asserts this signal active (low level) when it uses the data memory bus. * 0: Hold request * 1: No request Bus strobe signal output. This signal is asserted active (low level) when the PD77016 uses the external data bus. * 0: PD77016 uses the bus. * 1: PD77016 does not use the bus. Hold acknowledge signal output. This signal is asserted active (low level) when an external circuit requests HOLDRQ and then the external circuit is enabled to use the data memory bus. * 0: Enables the external circuit to use the data memory bus. * 1: Prevents the external circuit from using the data memory bus.
DA0-DA15
40 - 37 34 - 27 24 - 21
Output (3S)
D0-D15
60 - 57, 54 - 47, 44 - 41 17 16 6
I/O (3S)
MRD MWR WAIT
Output (3S) Output (3S) Input
HOLDRQ
7
Input
BSTB
18
Output
HOLDAK
19
Output
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when the external data memory is not accessed and when the bus is released (HOLDAK = 0).
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2.3 Pin Functions
(5) Serial interface
Pin name SCK1 Pin No. 65 I/O Input Function Serial #1 channel clock input. Signals related to serial input/output are sampled in synchronization with this signal. Serial #1 channel output request signal output. This signal is asserted active (high level) before serial data is output. * 0: Serial data is not output. * 1: Serial data is output. Serial #1 channel output enable signal input. This signal is asserted active (high level) to inform the PD77016 that the external circuit is ready to accept serial output data. * 0: Not ready to accept serial data output. * 1: Ready to accept serial data output Serial #1 channel data output. This signal is output in synchronization with the rising of SCK1. Serial #1 channel input enable signal input. This signal is asserted active (high level) to inform the PD77016 that the external circuit is ready to supply serial data. * 0: Not ready to supply serial data. * 1: Ready to supply serial data. Serial #1 channel data input. This signal is input in synchronization with the falling of SCK1. Serial #1 channel input acknowledge signal output. This signal informs the external circuit that the PD77016 is ready to input serial data. * 0: Not ready to accept serial data input. * 1: Ready to accept serial data input. Serial #2 channel clock input. Signals related to serial input/output are sampled in synchronization with this signal. Serial #2 channel output request signal output. This signal is asserted active (high level) before serial data is output. * 0: Serial data is not output. * 1: Serial data is output.
SORQ1
68
Output
SOEN1
69
Input
SO1 SIEN1
67 64
Output (3S) Input
SI1 SIAK1
63 66
Input Output
SCK2
76
Input
SORQ2
73
Output
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when data output have been finished or RESET is input.
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Chapter 2 Pin Functions
2.3 Pin Functions
Pin name SOEN2
Pin No. 72
I/O Input
Function Serial #2 channel output enable signal input. This signal is asserted active (high level) to inform the PD77016 that the external circuit is ready to accept serial data output. * 0: Not ready to accept serial data output. * 1: Ready to accept serial data input Serial #2 channel data output. This signal is output in synchronization with the rising of SCK2. Serial #2 channel input enable signal. This signal is asserted active (high level) to inform the PD77016 that the external circuit is ready for supplying serial data. * 0: Not ready to supply serial data * 1: Ready to supply serial data Serial #2 channel data input. This signal is input in synchronization with the falling of SCK2. Serial #2 channel input acknowledge signal output. This signal informs the external circuit that the PD77016 is ready to input serial data. * 0: Not ready to accept serial data input. * 1: Ready to accept serial data input.
SO2 SIEN2
74 77
Output (3S) Input
SI2 SIAK2
78 75
Input Output
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when data output have been finished or RESET is input.
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2.3 Pin Functions
(6) Host interface
Pin name HA1 Pin No. 83 I/O Input Function Specifies the register to be accessed by HD0 through HD7. * 0: When the PD77016 is read (HRD = 0), the host transmission data register (HDT (out)) is accessed: when it is written (HWR = 0), the host receive data register (HDT (in)) is accessed. * 1: The host interface status register (HST) is accessed. Specifies the register to be accessed by HD0 through HD7. * 0: Bits 7 through 0 of HST, HDT (out), and HDT (in) are accessed. * 1: Bits 15 through 8 of HST, HDT (out), and HDT (in) are accessed. Chip select input. Host read input. Pulse read from the host. Data is output in synchronization with the falling of this signal. Host write input. Pulse written from the host. Data is input in synchronization with the rising of this signal. Host read enable output. When this signal is active (low level), the host can access the PD77016 for read. * 0: Host can access for read. * 1: Host cannot access for read. Host write enable output. When this signal is active (low level), the host can access the PD77016 for write. * 0: Host can access for write. * 1: Host cannot access for write 8-bit host data bus
HA0
82
Input
HCS HRD HWR HRE
79 80 81 92
Input Input Input Output
HWE
93
Output
HD0-HD7
91-84
I/O (3S)
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when host does not access the PD7701x's host interface.
(7) I/O port
Pin name P0-P3 Pin No. 12-9 I/O I/O Function General-purpose I/O port. Each pin can be set in the input or output mode independently by PCD (port command register). Data is input or output via PCD and PDT (port data register).
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2.3 Pin Functions
(8) External instruction memory interface
Pin name IA0-IA15 Pin No. 120 - 117, 114 - 107, 104 - 101 I/O Output (3S) Function External instruction memory address bus. Even when the internal instruction memory of the PD77016 is accessed, the address internally accessed is output to an external device. At this time, the data output from the external instruction memory is ignored. 32-bit instruction input
ID0-ID31
159 - 152, 149 - 142, 139 - 132, 128 - 121, 129
I/O (3S)
PWR
Output (3S)
Program memory write strobe. While the PD77016 is performing a boot operation, this signal is used as a write strobe to the external instruction memory when the program is loaded to the external instruction memory, instead of the internal memory.
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when the hardware reset signal is input.
(9) Debug interface
Pin name TDO TICE TCK TDI TMS Pin No. 96 97 98 99 100 I/O Output Output Input Input Input Function Used for debugging. Used for debugging. Used for debugging. Used for debugging. Used for debugging.
(10) Other
Pin name NC Pin No. 160 I/O -- Function Non-connection
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2.3 Pin Functions
2.3.2 Pin function of PD77015, 77017, 77018, 77018A, and 77019
Because the pin numbers differ depending on the package, refer to the pin numbers of the package used.
(1) Power supply
Pin name VDD Pin No. TQFP BGA 11, 21, 31, 37, 43, 56, 69, 86, 97 A3, A8, B2 B3, B10, C2, C3, C11, C12, D12, D13, F1, J13, K1, K2, L2, N5, N7, N9 B4, C5, C9, F11, G2, K3, K11, K12, L4, L6, L8, L11, M4, M10, M11 I/O -- Function +3-V power supply. Connect all these pins to a +3-V power supply.
GND
10, 20, 30, 36, 42, 55, 68, 83, 96
--
Ground. Connect all these pins to 0 V.
(2) System control
Pin name X1 85 Pin No. TQFP BGA C8 Input Clock input or crystal oscillator connection. Use this pin to input an external clock. Always supply the clock in normal device operation. In the stop mode, however, clock supply may be stopped. Crystal oscillator connection. When using an external clock, leave this pin open. Always leave this pin on the PD77019-013 open. Internal system clock output. Output synchronized with the clock input or crystal oscillation frequency supplied to X1. Use this pin when processing in synchronization with the instruction cycle of the PD77015, 77017, 77018, 77018A, or 77019 is necessary for the external circuit. Output of the internal system clock can be also suppressed (fixed to low level) by mask option. Internal system reset signal input. Initializes the hardware of the device. Be sure to input the RESET signal after power application to the device. I/O Function
X2
84
B8
--
CLKOUT
87
B7
Output
RESET
1
C1
Input
(3) Interrupt
Pin name Pin No. TQFP BGA E2, D1, D3, D2 I/O Input Function External interrupt inputs. These interrupt inputs can be masked and are detected at the falling edge. If interrupts conflict, a one level recording function is available for each input. 41
INT1-INT4 5-2
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2.3 Pin Functions
(4) External data memory interface
Pin name X/Y Pin No. TQFP BGA 7 E1 I/O Output (3S) Function Memory space select signal output. * 0: Selects X memory space. * 1: Selects Y memory space. The X and Y memory spaces of an external memory cannot be accessed at the same time. Address bus for external data memory. * Accesses an external memory. When the external memory is not accessed, this bus keeps outputting the address of the external memory location accessed last. If the external memory has never been accessed after reset, it outputs a low level (0x0000). 16-bit data bus. Accesses an external memory.
DA0-DA13 25 - 22, 19 - 12 8, 9
M3 - M1, L1, J1, J3, J2, H1, H3, H2, G1, G3, F3, F2
Output (3S)
D0-D15
47 - 44, 41 - 38, 35 - 32, 29 - 26
L10, N10, L9, M9, N8, M8, L7, M7, N6, M6, L5, M5, N4, N3, L3, N2 C4 A4 B1
I/O (3S)
MRD MWR WAIT
98 95 100
Output (3S) Output (3S) Input
Read output. External memory read. Write output. External memory write. Wait signal input. Wait cycles specified by DWTR (data memory wait cycle register) are inserted when the external data memory is accessed, and this signal is sampled at the end of the wait cycles. While the WAIT signal is active (low level), wait cycles are unconditionally inserted. * 0: Wait * 1: No wait (However, if the wait cycle specified by DWTR has been completed.) Hold request signal input. An external circuit asserts this signal active (low level) when it uses the data memory bus. * 0: Hold request * 1: No wait Bus strobe signal output. This signal is asserted active (low level) when the PD77015, 77017, 77018, 77018A, or 77019 uses the external data bus. * 0: PD77015, 77017, 77018, 77018A, or 77019 uses the bus. * 1: PD77015, 77017, 77018, 77018A, or 77019 does not use the bus. Hold acknowledge signal output. This signal is asserted active (low level) when an external circuit requests HOLDRQ and then the external circuit is enabled to use the data memory bus. * 0: Enables the external circuit to use the data memory bus. * 1: Does not enable the external circuit to use the data memory bus.
HOLDRQ
93
B5
Input
BSTB
99
A2
Output
HOLDAK
94
A5
Output
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when the external data memory is not accessed and when the bus is released (HOLDAK = 0).
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(5) Serial interface
Pin name SCK1 Pin No. TQFP BGA 50 M12 I/O Input Function Serial #1 channel clock input. Signals related to serial input/output are sampled in synchronization with this signal. Serial #1 channel output request signal output. This signal is asserted active (high level) before serial data is output. * 0: Serial data is not output. * 1: Serial data is output. Serial #1 channel output enable signal input. This signal is asserted active (high level) to inform the PD77015, 77017, 77018, 77018A, or 77019 that the external circuit is ready to accept serial output data. * 0: Not ready to accept serial data output. * 1: Ready to accept serial data output Serial #1 channel data output. This signal is output in synchronization with the rising of SCK1. Serial #1 channel input enable signal input. This signal is asserted active (high level) to inform the PD77015, 77017, 77018, 77018A, or 77019 that the external circuit is ready to supply serial data. * 0: Not ready to supply serial data. * 1: Ready to supply serial data. Serial #1 channel data input. This signal is input in synchronization with the falling of SCK1. Serial #1 channel input acknowledge signal output. This signal informs the external circuit that the PD77015, 77017, 77018, 77018A or 77019 is ready to input serial data. * 0: Not ready to accept serial data input. * 1: Ready to accept serial data input. Serial #2 channel clock input. Signals related to serial input/output are sampled in synchronization with this signal.
SORQ1
53
L13
Output
SOEN1
54
K13
Input
SO1
52
M13
Output (3S) Input
SIEN1
49
N12
SI1 SIAK1
48 51
N11 L12
Input Output
SCK2
59
H12
Input
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when data output have been finished or RESET is input.
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2.3 Pin Functions
Pin name SOEN2
Pin No. TQFP BGA 57 J12
I/O Input
Function Serial #2 channel output enable signal input. This signal is asserted active (high level) to inform the PD77015, 77017, 77018, 77018A, or 77019 that the external circuit is ready to accept serial data output. * 0: Not ready to accept serial data output. * 1: Ready to accept serial data input Serial #2 channel data output. This signal is output in synchronization with the rising of SCK2. Serial #2 channel input enable signal. This signal is asserted active (high level) to inform the PD77015, 77017, 77018, 77018A, or 77019 that the external circuit is ready to supply serial data. * 0: Not ready to supply serial data * 1: Ready to supply serial data Serial #2 channel data input. This signal is input in synchronization with the falling of SCK2.
SO2
58
J11
Output (3S) Input
SIEN2
60
H13
SI2
61
H11
Input
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when data output have been finished or RESET is input.
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2.3 Pin Functions
(6) Host interface
Pin name HA1 Pin No. TQFP BGA 82 A9 I/O Input Function Specifies the register to be accessed by HD0 through HD7. * 0: When the PD77015, 77017, 77018, 77018A, or 77019 is read (HRD = 0), the host transmission data register (HDT (out)) is accessed: when it is written (HWR = 0), the host receive data register (HDT (in)) is accessed. * 1: The host interface status register (HST) is accessed. Specifies the register to be accessed by HD0 through HD7. * 0: Bits 7 through 0 of HST, HDT (out), and HDT (in) are accessed. * 1: Bits 15 through 8 of HST, HDT (out), and HDT (in) are accessed. Chip select input Host read input. Pulse read from the host. Data is output in synchronization with the falling of this signal. Host write input. Pulse written from the host. Data is input in synchronization with the rising of this signal. Host read enable output. When this signal is active (low level), the host can access the PD77015, 77017, 77018, 77018A, or 77019 for read. * 0: Host can access for read. * 1: Host cannot access for read. Host write enable output. When this signal is active (low level), the host can access the PD77015, 77017, 77018, 77018A, or 77019 for write. * 0: Host can access for write. * 1: Host cannot access for write 8-bit host data bus
HA0
81
B9
Input
HCS HRD
78 79
A11 A10
Input Input
HWR
80
C10
Input
HRE
66
F13
Output
HWE
67
E13
Output
HD0-HD7
77-70
A12, B11 - B13, D11, C13, E11, E12
I/O (3S)
Remark "3S" in the "I/O" column of the above table stands for three-state pin, and these pins go into a highimpedance state when the host does not access the PD7701x's host interface.
(7) I/O port
Pin name P0-P3 Pin No. TQFP BGA 65-62 F12, G11, G13, G12 I/O I/O Function General-purpose I/O port. Each pin can be set in the input or output mode independently by PCD (port command register). Data is input or output via PCD and PDT (port data register).
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(8) Debug interface
Pin name TDO TICE TCK TDI TMS Pin No. TQFP BGA 88 89 90 91 92 A7 C7 B6 A6 C6 I/O Output Output Input Input Input Function Used for debugging. Used for debugging. Used for debugging. Used for debugging. Used for debugging.
(9) Others
Pin name I.C. Pin No. TQFP BGA 6 E3 I/O -- Function Internally connected: Open this pin.
Caution
Be sure not to connect the I.C. pin. If any signal is applied to the I.C. pin or if the I.C. pin status is read out, normal operation of the device is not guaranteed.
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2.4 Handling of Unused Pins
2.4
Handling of Unused Pins
It is recommended that unused pins be connected as shown in the table below.
Table 2-1. Handling of Unused Pins
Pin
INT1-INT4 X/Y DA0-DA15 D0-D15Note 1 MRD, MWR WAIT HOLDRQ BSTB HOLDAK SCK1, SCK2 SI1, SI2 SIEN1, SIEN2 SOEN1, SOEN2 SORQ1, SORQ2 SO1, SO2 SIAK1, SIAK2 HA0, HA1 HCS, HRD, HWR HRE, HWE HD0-HD7Note 2 P0-P3 ID0-ID31 IA0-IA15 PWR TCK TDO,TICE TMS, TDI CLKOUT
Direction
I O O I/O O I I O O I I I I O O O I I O I/O I/O I/O O O I O I O
Recommended Connection
Connect to VDD. Open Open Connect to VDD via pull-up resistor, or to GND via pull-down resistor. Open Connect to VDD. Connect to VDD. Open Open Connect to VDD or GND. Connect to VDD or GND. Connect to GND. Connect to GND. Open Open Open Connect to VDD or GND. Connect to VDD. Open Connect to VDD via pull-up resistor, or to GND via pull-down resistor. Connect to VDD via pull-up resistor, or to GND via pull-down resistor. Connect to VDD via pull-up resistor, or to GND via pull-down resistor. Open Open Connect to GND via pull-down resistor. Open Open (pulled up internally) Open
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2.4 Handling of Unused Pins
Remark I: Input pin, O: Output pin, I/O: I/O pin Notes 1. These pins may be left open if the external data memory is not accessed by program. To reduce the current consumption by using the halt mode or stop mode, however, observe the recommended connection. 2. These pins may be left open if HCS, HRD, and HWR are fixed to high level. To reduce the current consumption by using the halt mode or stop mode, however, observe the recommended connection.
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Chapter 3
Architecture
This chapter describes the architecture of the PD7701x family by dividing it into several physical blocks and explaining the functions of each block. The overall organization is described in section 3.1, and the details (units) are then described in section 3.2 and following sections.
1 2 3 4 5 6 A B C
3.1
Overall Block Organization
This section divides the physical structure of the PD7701x family into several functional blocks for explanation. The PD7701x family consists of the following internal units: * Buses (main bus, X data bus, and Y data bus) Refer to section 3.2 "Buses." * System control units Refer to section 3.3 "System Control Units." * Program control unit Refer to section 3.4 "Program Control Unit." * Data addressing unit Refer to section 3.5 "Data Addressing Unit." * Operation unit Refer to section 3.6 "Operation Unit." * Peripheral unit Refer to section 3.7 "Peripheral Unit." Figure 3-1 illustrates the block organization. Refer to the corresponding sections for the functions of the respective blocks.
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3.1 Overall Block Organization
Figure 3-1. Overall Block Organization
X data bus (See section 3.2.2) External data memory interface Peripheral bus Y data bus (See section 3.2.2)
Serial interface #1
Peripheral unit (See section 3.7)
Serial I/O
Data addressing unit (See section 3.5) X data memory Y data memory
Operation unit (See section 3.6) R0-R7 MAC, ALU, BSFT
Serial interface #2
Wait controller
Host interface
Host I/O
General-purpose I/O port Debug interface (JTAG)
Port
Main bus (See section 3.2.1)
JTAG I/O
Program control unit (See section 3.4)
Instruction memory Program execution control PC stack Interrupt control Flow control LOOP control stack
External instruction memory External interrupt INT1-INT4 System clock Instruction execution pipeline
Reset
Standby
System control unit (See section 3.3) Clock, Reset Clock generator
External
Internal
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3.2 Buses
3.2
Buses
A bus transfers data between external devices and the processor. The PD7701x family is provided with the following three types of buses: * Main bus * X data bus * Y data bus
3.2.1 Main bus
(1) Function
This 16-bit bus connects the general-purpose registers (R0-R7) and control registers, etc. It transfers data when the following instructions are executed:
* Register-to-register transfer instruction This instruction transfers data between the L part of a general-purpose register and a nongeneral-purpose register. These registers are listed in Table 3-1. Note that this instruction transfers only the L part of a general-purpose register. For details, refer to "PD7701x Family User's Manual Instructions."
Caution
A general-purpose register consists of 40 bits. These 40 bits are divided into three parts: L (lower 16 bits), H (16 bits in the middle), and E (higher 8 bits). For details, refer to section 3.6.2 "General-purpose registers and data formats."
* Immediate value setting instruction This instruction sets immediate data to a specified register. Of the registers listed in Table 3-1, the following can be specified. * General-purpose registers (L part (R0L-R7L) only) * Data pointers (DP0-DP7) * Index registers (DN0-DN7) * Modulo registers (DMX, DMY) For the details of this instruction, refer to "PD7701x Family User's Manual Instructions."
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3.2 Buses
(2) Registers connected to main bus
The table shown below lists the registers connected to the main bus.
Table 3-1. Registers Connected to Main Bus
Register name General-purpose register Data pointer Index register Modulo register Stack Stack pointer Loop counter Loop stack (LSTK) Loop stack pointer Status register Interrupt enable flag stack register Error status register Assembler-reserved name R0L-R7L (L part of R0-R7) DP0-DP7 DN0-DN7 DMX, DMY STK SP LC LSR1, LSR2, LSR3 LSP SR EIR ESR Load (L)/store (S) L/S L/S L/S L/S L/S L/S L/S L/S L/S L/S L/S L/S
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3.2 Buses
3.2.2 Data bus
(1) Function
This 16-bit bus connects the general-purpose registers, X and Y data memories, and internal peripherals. It transfers data when the following instructions are executed. * Parallel load/store instruction * Partial load/store instruction * Direct addressing load/store instruction * Immediate value index load/store instruction For the details of the load/store instruction, refer to "PD7701x Family User's Manual Instructions." The data bus is classified into X data bus, Y data bus, and peripheral bus. The logical and physical relations among these buses are shown in Table 3-2.
Table 3-2. Functional Block and Bus
Functional block Internal memory peripherals Relations among X data bus, Y data bus, and peripheral bus X and Y data buses are logically and physically separated. Therefore, both the X and Y data buses are validated for transfer by a single instruction. X and Y data buses are logically and physically connected. Even when a peripheral-related register is accessed from X or Y memory space, therefore, the same peripheral register is accessed as long as the address is the same. At this time, however, the peripheral register cannot be accessed simultaneously from the X and Y data memory spaces with a single instruction. Although the X and Y data buses are logically separated, they are physically common. Therefore, the X and Y external memories cannot be accessed simultaneously with a single instruction.
Internal peripheral
External memory
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3.2 Buses
(2) X data bus
This 16-bit bus connects the general-purpose registers, X data memory, and the bus from the internal peripherals. This bus transfers data when the following instructions are executed: * Parallel load/store instruction (for X memory) * Partial load/store instruction (for X memory) * Direct addressing load/store instruction (for X memory) * Immediate value index load/store instruction (for X memory)
Cautions 1. Although the X and Y data buses are separated inside the device, a single data bus is commonly used externally. Thus, an instruction that accesses both external memories cannot be executed in the same instruction cycle. 2. The same peripheral register is accessed for internal peripheral regardless of whether the X or Y memory is accessed, as long as the address is the same. 3. Even in the case of 2 above, a peripheral register cannot be accessed from both the X and Y memory spaces in the same instruction cycle.
The table shown below shows the registers and memories connected to the X data bus.
Table 3-3. Registers and Memories Connected to X Data Bus
Register/memory name General-purpose register Assembler-reserved name R0-R7 R0E-R7E R0H-R7H R0L-R7L R0EH-R7EH -- -- -- -- Load (L)/store (S) L/S
X internal RAM X internal ROM (not for the PD77016) External memory Internal peripheral
L/S from ROM to bus only L/S L/S
Caution
A general-purpose register consists of 40 bits. These 40 bits are divided into three parts: L (lower 16 bits), H (16 bits in the middle), and E (higher 8 bits). Any of these parts can be specified for transfer. For details, refer to section 3.6.2 "General-purpose registers and data formats."
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3.2 Buses
(3) Y data bus
This 16-bit bus connects the general-purpose registers, Y data memory, and the bus from the internal peripherals. This bus transfers data when the following instructions are executed: * Parallel load/store instruction (for Y memory) * Partial load/store instruction (for Y memory) * Direct addressing load/store instruction (for Y memory) * Immediate value index load/store instruction (for Y memory)
Cautions 1. Although the X and Y data buses are separated inside the device, a single data bus is commonly used externally. Thus, an instruction that accesses both external memories cannot be executed in the same instruction cycle. 2. The same peripheral register is accessed for internal peripheral units regardless of whether the X or Y memory is accessed, as long as the address is the same. 3. Even in the case of 2 above, a peripheral register cannot be accessed from both the X and Y memory spaces in the same instruction cycle.
Table 3-4 shows the registers and memories connected to the Y data bus.
Table 3-4. Registers and Memories Connected to Y Data Bus
Register/memory name General-purpose register Assembler-reserved name R0 - R7 R0E - R7E R0H - R7H R0L - R7L R0EH - R7EH -- -- -- -- Load (L)/store (S) L/S
Y internal RAM Y internal ROM (not for the PD77016) External memory Internal peripheral
L/S from ROM to bus only L/S L/S
Caution
A general-purpose register consists of 40 bits. These 40 bits are divided into three parts: L (lower 16 bits), H (16 bits in the middle), and E (higher 8 bits). Any of these parts can be specified for transfer. For details, refer to section 3.6.2 "General-purpose registers and data formats."
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3.2 Buses
(4) Peripheral bus
This 16-bit bus connects the internal peripheral registers and the X/Y data buses. The peripheral registers are commonly mapped on the X/Y memory spaces. Data is transferred by executing the following instructions. * Parallel load/store instruction (for peripheral register) * Partial load/store instruction (for peripheral register) * Direct addressing load/store instruction (for peripheral register) * Immediate value index load/store instruction (for peripheral register) For the details of the peripheral bus, refer to section 3.7 "Peripheral Units."
Cautions 1. The same peripheral register is accessed for internal peripheral regardless of whether the X or Y memory is accessed, as long as the address is the same. 2. Even in the case of 1 above, a peripheral register cannot be accessed from both the X and Y memory spaces in the same instruction cycle.
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3.3 System Control Units
3.3
System Control Units
The following basic functions, which support the digital signal processor operations of the PD7701x family, are called system control units: * Clock generator * Reset function * Pipeline architecture * Standby function
3.3.1 Clock generator
The clock generator is a circuit that generates and controls the system clock supplied to the CPU. The configuration of this circuit differs between the PD77016 and PD77015/77017/ 77018/77018A/77019.
(1) PD77016
An internal system clock is generated from an external clock input to the CLKIN pin. This internal system clock serves as a reference of the internal basic timing of the device. The internal system clock is also output from the CLKOUT pin to establish synchronization between external devices and the PD77016. At this time, the frequency ratio of the external clock to the internal system clock is 2 : 1. Figure 3-2 shows the clock circuit, and Figure 3-3 shows the timing requirements.
Figure 3-2. Clock Circuit of PD77016
Divider
CLKIN
1/2
Internal system clock
CLKOUT
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Figure 3-3. Clock Timing of PD77016
tcCI twCIH CLKIN tcCO twCO CLKOUT twCO trfCO trfCO twCIL trfCI trfCI
(2) PD77015, 77017, 77018, 77018A, 77019
[External clock input] An internal system clock is generated from an external clock input to the X1 pin. This internal system clock serves a reference of the internal basic timing. The internal system clock is also output from the CLKOUT pin to establish synchronization between external devices and PD77015, 77017, 77018, 77018A, 77019 (this function can be disabled by mask option). The external clock is multiplied by PLL. The multiple can be specified by mask option. At this time, the frequency ratio of the external clock to the internal system clock is selected from the following alternatives: * 1 (external) : 1 (internal) * 1 (external) : 2 (internal) * 1 (external) : 3 (internal) (for PD77018A and 77019 only) * 1 (external) : 4 (internal) * 1 (external) : 8 (internal) Assuming that the internal system clock frequency is 33 MHz, for example, the input clock frequencies are as follows: * 1 : 1 --> external 33 MHz * 1 : 2 --> external 16.5 MHz * 1 : 3 --> external 11 MHz (for PD77018A and 77019 only) * 1 : 4 --> external 8.25 MHz * 1 : 8 --> external 4.125 MHz
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[When using crystal resonator] If a frequency ratio of 1 : 1 is selected by mask option, a crystal resonator can be connected across the X1 and X2 pins to configure a self-oscillation circuit. Figure 3-4 shows the clock circuit of the PD77015, 77017, 77018, 77018A, and 77019 and Figure 3-5 shows the timing. For how to order mask option, refer to Appendix B "Ordering Information."
Figure 3-4. Clock Circuit of PD77015, 77017, 77018, 77018A, 77019
(a) To supply external clock
STOP mode
C1 X1
(b) To use crystal resonator
STOP mode
External clock NU CLKOUT
X1 X2
PLL control circuit
Internal system clock
X2 C2
System clock oscillation circuit
Internal system clock
CLKOUT
Remark NU: Not use (leave this pin open.)
Cautions 1. Be sure to specify a multiple of 1 by mask option when using a crystal resonator with the PD77015, 77017, 77018, 77018A, or 77019. The processor does not operate with any other multiples. 2. The multiplication factor of the mask option of the PD77019-013 is fixed to 4. The crystal resonator cannot be used with this model.
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(3) Clock operation in standby mode
The operating status of the system clock is in the HALT/STOP mode is as follows:
STOP mode HALT mode enable to stop 1/8 of ext. clock x PLL factor 1/8 of crystal resonator frequency
PD77016 PD77015/77017/77018
/77018A/77019 ext. clock + PLL crystal resonator
--
stops stops
Figure 3-5. Clock Timing of PD77015, 77017, 77018, 77018A, 77019
tcCX twCXH X1 twCXL
trfCX
trfCX
tcC Internal clock
tcCO twCO CLKOUT twCO
trfCO
trfCO
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3.3.2 Reset function
The hardware of the device is reset when the signal input to the RESET pin is activated (low level). The purpose of resetting is to correctly initialize the device before program execution. The registers and pins to be initialized, and their initial values are shown in Tables 3-5 to 3-7. Figure 3-6 shows the reset timing. For details of how the value of each pin and each register changes depending on the respective boot operations, refer to Chapter 4 "Boot Function."
Table 3-5. CPU Registers to Be Initialized and Their Initial Values
Register name SR Initial value 0xF000 Description Interrupts of all sources are enabled but interrupts are disabled generally at all the present and past levels. Loop operation is not performed. Address 0 is a boot area and execution branches to address 0x200 after boot processing has ended. Therefore, the reset entry as a user area is at address 0x200. -- Indicates that loop operation is not performed. The count value itself is undefined. -- Indicates that repeat operation is not performed. The count value itself is undefined. Indicates that all the interrupts are disabled at all the present and past levels. --
PC
0
SP LC LSP RC EIR ESR
0 0b1xxx xxxx xxxx xxxx 0 0b1xxx xxxx xxxx xxxx 0xFFFF 0
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Table 3-6. Initialized Memory-mapped Registers and Their Initial Values
Register name SST1, SST2 Initial value 0x0002 Description The serial interface is initialized as follows: * MSB first for both input and output * 16-bit length for both input and output * Wait is not used for load/store of SDT * Status transition mode * Clears error flag of SDT load/store * Data store to SDT enabled * No data to be loaded from SDT PCD 0x0000 The I/O ports are initialized as follows: * No bit manipulation * No mode setting HST 0x0301 The host interface is initialized as follows: * Wait is not used for HDT access * Disables HRE and HWE functions * Clears UF0 and UF1 to zero * Clears error flag for host read/write * Clears error flag of HDT load/store * Disables read from host * Enables write to host
Table 3-7. Initialized Pins and Their Initial Statuses
Pin name X/Y DA0-DA15 D0-D15 IA0-IA15 Note 2 ID0-ID31 Note 2 PWR Note 2 MRD, MWR, BSTB SORQ1, SORQ2, SIAK1, SIAK2 SO1, SO2 HRE, HWE P0-P3 TICE Initial Status Low-level outputNote 1 Low-level outputNote 1 High-impedance Low-level output (high-impedance during reset) High-impedance High-level output (high-impedance during reset) High-level output Note 1 Low-level output High-impedance High-level output Input status Low-level output
Notes 1. These pins go into a high-impedance state when the bus is released (HOLDAK = 0). The bus can be released even during reset when HOLDRQ = 0. 2. PD77016 only.
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Figure 3-6. Reset Timing
tw (RL) RESET trec (R)
3.3.3 Pipeline architecture
The PD7701x family employs pipeline architecture to enhance the execution speed. Generally, one instruction completes its processing via several machine cycles each of which performs elemental processing. The instructions of the PD7701x family have the following three machine cycles: F : instruction fetch cycle Reads an op code from the instruction memory. D : decode cycle Decodes the read op code. E : execution cycle Executes the decoded result. The part that executes each machine cycle is called a pipeline stage. Each stage independently completes processing with the same number of clocks (1 cycle). Therefore, an instruction under execution enters stages one after another without wait time. In addition, three instructions can exist in the respective three stages at the same time. In other words, it seems as if one instruction were processed with the execution time of one stage as long as the instruction passes through the pipelines without any instruction stream fault. The number of clock cycles in one stage is called one instruction cycle, which is 30 ns in the case that operates with a 33-MHz clock.
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Figure 3-7 provides images of pipeline operation. Figure 3-7(a) is a conceptional illustration that shows the flow of executed instructions when viewed from each pipeline stage. Figure 3-7(b) shows the sequence in which instructions are executed in pipeline, from the viewpoint of each instruction.
Figure 3-7. Pipeline Image (a) Pipeline image 1
1 instruction cycle
Time
F cycle
Instruction J
D cycle
Instruction I
E cycle
Instruction H
Instruction K
Instruction J
Instruction I
Instruction L
Instruction K
Instruction J
(b) Pipeline image 2
Time PC n F1 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 D1 F2 E1 D2 F3 E2 D3 F4 E3 D4 E4
Instruction sequence
Instruction 1 (address n) Instruction 2 (address n + 1) Instruction 3 (address n + 2) Instruction 4 (address n + 3)
Remarks Fn: fetch cycle of instruction n Dn: decode cycle of instruction n En: execution cycle of instruction n
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(1) Successive MAC, ALU, Barrelshifter operations
When an instruction performing arithmetic/logic operations uses the result of the operation executed by the preceding instruction as an input operand, the result of the operation is written to a general-purpose register and, at the same time, input to the operation unit for the operation by the subsequent instruction. Consequently, programming can be done without having to be aware of the pipeline.
(2) Branch instruction
If a pipeline hazard occurs as a result of executing a branch instruction, the pipeline is replenished again with a NOP instruction inserted into the delay slot. Though the execution time is consequently extended, this does not cause erroneous application operation, and there is no need for users to consider the pipeline operation even in programming branch instructions. For further details about pipeline timing with branch instructions refer to section 3.4.2 "Program execution control block".
Caution
The delay due to the processing of the pipeline must be taken into account in the following cases: * Instructions that control interrupts (by setting EIR, etc.) requires two instruction cycles to update the interrupt control information (refer to section 3.4.4 "Interrupt"). * When a value is set to DPn by using a Inter-register transfer instruction or immediate value setting instruction, the memory cannot be accessed by using the value set to DPn as an address until the instruction that follow the instruction that has set a value to DPn. Example: inst#1 DP0 = 0x0100 inst#2 NOP inst#3 R0L = *DP0 ; ; DP0 cannot be used here! ;
* The branch instruction cannot be written within three instructions before the loop end (refer to section 3.4.3 "Flow control block").
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3.3.4 Standby function
The PD7701x family is provided with a standby function that stops the device to reduce the current consumption. The device enters a standby status when an appropriate instruction is executed. This status is called a standby mode. The standby mode is set by two types of instructions: HALT and STOP. The PD77016 does not have the STOP mode.
(1) Standby mode by HALT instruction
This standby mode is common to all models of the PD7701x family and is called HALT mode. This mode is set by the HALT instruction. The current consumption of the device in the HALT mode is reduced. The HALT mode is set or released as follows: (a) The HALT mode is set by executing the HALT instruction. (b) At this time, the registers and internal memory retain the status immediately before the HALT mode is set, and the current consumption of the device decreases. The status of each pin of the device is shown in Table 3-8. (c) This mode is released by using an external/internal interrupt (which is not masked) or hardware reset (refer to section 3.4.4 "Interrupt"). (d) When the HALT mode has been released by using an interrupt, the return address to which execution returns after the interrupt processing is the address of the instruction next to the HALT instruction. Before the HALT mode is released, a heat-up cycle (NOP) of one instruction cycle is inserted so that the system can restore from the power-down status. (e) For the PD77016 only in this mode, the external clock may be stopped (fixed to high or low level). To release this mode by using an interrupt, however, the clock must be restored before the interrupt is executed.
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Table 3-8. Pin Status in HALT Mode
Pin name CLKOUTNote X/Y IA0 - IA15 DA13 - DA0 D15 - D0 MRD/MWR HOLDAK BSTB SORQ1, SIAK1, SO1, SO2 HRE, HWE, HD7 - HD0 P3 - P0 TDO, TICE High impedance Low level High impedance When HOLDRQ is Active (low level) When HOLDRQ is Inactive (high level)
x1/8 clock output Low level
Retains status immediately before High impedance Retains status immediately before High impedance High level High level High level Retains status immediately before
Caution
Fix the input pins and pins that go into a high-impedance state in the HALT mode to the high or low level.
Note With the PD77015, 77017, 77018, 77018A, and 77019, if CLKOUT is activated low by mask option, it remains low.
Figure 3-8 (a) illustrates how the HALT mode is released by using an interrupt. Figure 3-8 (b) and (c) show the timings of setting and releasing the HALT mode, respectively.
Figure 3-8. HALT Mode (a) Releasing from HALT mode (by using interrupt)
HALT
Stop status
External interrupt input (INT1-INT4) or internal interrupt input
0x210 0x214 0x218 0x21C
Interrupt processing
***
RETI
Instruction next to HALT instruction
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(b) Timing of setting HALT mode
Clock if1 id1 halt
if2
nop
if2 Pipeline stops Power-down status
nop
Clock can be stopped from here (only PD77016).
Remarks if : id:
instruction fetch instruction decode
(c) Timing of releasing HALT mode
Clock
if2 Interrupt processing instruction #1 Interrupt processing instruction #2 pc Pipeline stops Power-down status INT accept if2
nop
heat
iif1
iid1
iex1
iif2 iif1 iif2
iid2
iex2
Remarks ifn : instruction fetch iifn : interrupt instruction fetch iidn : interrupt instruction decode iexn: interrupt instruction execution
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(2) Standby mode by STOP instruction
This mode, called STOP mode, can be set with the PD77015/77017/77018/77018A/77019 only. The STOP mode is set by executing the STOP instruction. In this mode, the current consumption of the device is reduced to several tens of A. The STOP mode is set or released as follows: 1. The STOP mode is set when the STOP instruction is executed. 2. At this time, the status of each pin of the device is as shown in Table 3-9. 3. The clock circuit and PLL stop, and the current consumption of the device is reduced to several tens of A or less. 4. The device is released from the STOP mode only by hardware reset. At this time, PLL takes some time to be released from the mode. Therefore, assert the reset signal active for at least 1 ms.
Table 3-9. Pin Status in STOP Mode
Pin name CLKOUT X/Y DA13 - DA0 D15 - D0 MRD/MWR HOLDAK BSTB SORQ1, SIAK1, SO1, SO2 HRE, HWE, HD7 - HD0 P3 - P0 TDO, TICE High impedance Low level High impedance High impedance When HOLDRQ is Active (low level) When HOLDRQ is Inactive (high level) Low level Low level Retains status immediately before High impedance High level High level High level Retains status immediately before
Caution
Fix the input pins and pins that go into a high-impedance state in the STOP mode to the high or low level.
When the STOP mode is released by means of hardware reset, the output pins are initialized. Some output pins, however, are in the undefined status until the PLL of the device is stabilized, and their operation is not guaranteed. Table 3-10 shows the status of each output pin during the reset period following releasing the STOP mode.
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Table 3-10. Output Pin Status during Reset Period after Releasing STOP Mode
Pin name CLKOUT X/Y DA0-DA13 D0-D15 MRD MWR BSTB HOLDAK HD0-HD7 HRE HWE SO1, SO2 SIAK1 SORQ1 P0-P3
Note
Initialized status system clock Note low level 0x0000 high-impedance high level
Status during reset of STOP mode release undefined Note undefined
high-impedance high level
high-impedance low level
input mode
When CLKOUT is fixed to low level by mask option, low level is output in even status of Initializing or status during reset for releasing STOP mode.
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3.4
Program Control Unit
This unit controls program execution. Data can be loaded from or stored to the registers in this unit via the main bus. This unit plays a role in execution of the following instructions: * General instruction execution * Branch instruction * Hardware loop instruction * Interrupt (Although an interrupt is not an instruction, PC, STK, SP, SR, and EIR are automatically controlled by INTC.) Execution of these instructions is controlled by the following three blocks of the program control unit: * Program execution control block * Flow control block * Interrupt control block Section 3.4.1 "Block configuration" shows a detailed block diagram of the program control unit. Section 3.4.2 "Program execution control block" through section 3.4.4 "Interrupt" describe the details of the functions of the respective blocks.
3.4.1 Block configuration
Figure 3-9 shows the block configuration of the program control unit.
Figure 3-9. Program Control Unit
Main bus (16 bits)
16 16 16 16 16 16 16 16 16 16 (Note)
EIR [16]
SR [16]
SP [16] STK [16 x 15 levels]
LSA [16]
LEA [16]
LC [16]
LSP [16]
RC [16]
INTC
LSR1
LSR2 LSTK [48 x 4 levels]
LSR3 LRC
PC [16]
Interrupt control block
Program Instruction memory, execution external instruction memory control block (PD77016 only)
Flow control block
Note RC cannot directly transfer data via the main bus.
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3.4.2 Program execution control block
Program execution is controlled by the following registers: * Program counter (PC) * Stack (STK) * Stack pointer (SP)
(1) Program counter (PC)
This is a 16-bit register that holds the address of the instruction currently under execution when the program is executed. Therefore, the range of the value the PC can take is the entire memory space.
Caution
The PC can take any value as long as it is in the range of 16 bits, but the portion that is not defined as the instruction memory space or the portion that is reserved for the system must not be accessed.
(a) Instruction memory The instruction memory space of the PD7701x family is shown below.
Figure 3-10. Instruction Memory Space
PD77016
0xFFFF
PD77015
PD77017
PD77018, 77018A
PD77019Note
External instruction memory (48K words) 0x5000 0x4FFF 0x4000 0x3FFF System (14K words) 0x0800 0x07FF Internal instruction RAM (1.5K words) 0x0240 0x023F 0x0200 Vector area (64 words) 0x01FF System (256 words) 0x0100 0x00FF Boot-up ROM (256 words) 0x0000 0x0300 0x02FF
System (44K words)
System (24K words) System (36K words) 0xA000 0x9FFF Internal instruction ROM (24K words)
System (24K words)
0x7000 0x6FFF Internal instruction ROM (4K words) System (15.25K words)
Internal instruction RAM (256 words)
Internal instruction ROM (12K words) System (15.25K words)
Internal instruction RAM (256 words)
Internal instruction ROM (24K words)
System (15.25K words)
Internal instruction RAM (256 words)
0x1200 System (11.5K words) 0x11FF Internal instruction RAM (4K words) Vector area (64 words) System (256 words) Boot-up ROM (256 words)
Vector area (64 words) System (256 words) Boot-up ROM (256 words)
Vector area (64 words) System (256 words) Boot-up ROM (256 words)
Vector area (64 words) System (256 words) Boot-up ROM (256 words)
Caution No program or data must be stored to the addresses reserved for the system, nor must these addresses be accessed. If any of these addresses is accessed, normal operation of the PD7701x family is not guaranteed. Note The PD77019-013 does not have the internal ROM of the PD77019.
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(b) Internal instruction memory The PD7701x family is provided with ROM or RAM as an internal instruction memory. The capacity of the internal instruction memory differs depending on the model, as shown in Table 3-11. The internal ROM of the PD77019-013 cannot be used.
Table 3-11. Capacity of Internal Instruction Memory
Part number Internal ROM capacity None 4K words 12K words 24K words Internal RAM capacity 1.5K words 256 words
PD77016 PD77015 PD77017 PD77018 PD77018A PD77019
4 K words
(c) External instruction memory The PD7701x can be connected with an external instruction memory. The capacity of this external memory is shown in Table 3-12.
Table 3-12. Capacity of External Memory
Part number External instruction memory capacity 48K words None
PD77016 PD77015 PD77017 PD77018 PD77018A PD77019
(d) Interfacing external instruction memory The PD77016 can be connected with an external instruction memory. The application program, however, cannot handle the external instruction memory as data. The application program can access the external instruction memory only in the following two cases: * When the program has been booted from the data memory or the host interface to the external memory by using the internal reboot function (Refer to Chapter 4 "Boot Function.") * When execution is branched to the external instruction memory space by using a branch instruction The interface that connects an external instruction memory to the PD77016 is explained in the following sections.
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(e) Hardware for external instruction memory expansion The following pins are used for interfacing the external instruction memory: * IA0-IA15 : 16 bits of address lines that provide an instruction memory address. IA15 is the MSB, and IA0 is the LSB. * ID0-ID31 : 32-bit data bus that transfers instruction codes. ID31 is the MSB, and ID0 is the LSB. * PWR : Signal line that generates a write strobe signal to the instruction memory. Active low.
Table 3-13. Pin Statuses
Pin IA0-IA15 ID0-ID31 PWR I/O O I/O O During reset Hi-Z Hi-Z Hi-Z Initial after reset L Hi-Z H No external memory accesses Internal memory address currently accessed Hi-Z H
Figure 3-11 shows the operation timing.
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Figure 3-11. Instruction Memory Operation Timing (a) Read operation timing
CLKOUT
tdIA IA0-IA15 Hi-Z
thIA
tsuID
thID
ID0-ID31
tdIW PWR Hi-Z
RESET
(b) Write operation timing
CLKOUT thIA
IA0-IA15
tsIDW
thIDW
ID0-ID31
Hi-Z
Hi-Z
td (IAV-IWV) twIW PWR
tsuIW
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(f) Wait function of external instruction memory * IWTR (instruction memory wait cycle register) The external instruction memory interface does not have a hardware wait function that is effected through handshaking, but is provided with a programmable wait function that is controlled via software. An instruction memory wait cycle register (IWTR) is provided as one of the internal peripheral registers, and the predetermined number of wait cycles can be selected and set to this register by the application program. IWTR is a 16-bit register. The number of wait cycles, at what one wait cycle corresponds to one internal system clock cycle can be specified by setting bits 2 to 7 of this register. The three fields of this register, IB-ID fields, each consisting of 2 bits, correspond to three 16K-word banks which correspond to the external memory that accounts for the 3/4 of the 64K-word memory space, and wait cycles can be independently inserted to each of the three banks. Figure 3-12 illustrates the image of this control. Table 3-14 shows the relations between the value set to each field of IWTR and the number of wait cycles.
Figure 3-12. Instruction Memory Control Banks and IWTR Field Configuration
Instruction memory
0xFFFF ID field 16K words 0xC000 0xBFFF IC field 16K words 0x8000 0x7FFF IB field 16K words 0x4000 0x3FFF 0x0000 Internal instruction memory area 16K words
15 14 IWTR
13
12 11 --
10
9
8
7
6
5
4
3
2
1 --
0
ID field IC field IB field
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Table 3-14. Set Values of IWTR Fields and Number of Wait Cycles
Bits 0 0 No. of wait cycles 0 Remarks 1 cycle access: Connects SRAM with access time of 8 ns (at 33 MHz) 0 1 1 2 cycle access: Connects SRAM with access time of 35 ns (at 33 MHz) 1 0 3 4 cycle access: Connects SRAM with access time of 85 ns (at 33 MHz) 1 1 7 8 cycle access: Connects mask ROM with access time of 150 ns (at 33 MHz)
Cautions 1. Data written to bits 15 through 8, 1, and 0 are ignored. The contents of bits 15 through 8, 1, and 0 are undefined when they are read. 2. With the PD77015/77017/77018/77018A/77019, data written to IWTR is ignored, and undefined data is read from IWTR.
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* Timing of instruction memory wait controller Wait control to IWTR by using a store instruction becomes valid starting from instruction fetch immediately after the execution cycle of the store instruction. Figure 3-13 shows the timing.
Figure 3-13. Valid Timing of Instruction Memory Wait Control
Instruction storing data to IWTR
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
First instruction for which specification of IWTR is valid
if4
id4
ex4
Remarks if : instruction fetch id : instruction decode ex: instruction execution
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* External instruction memory interface example Based on the above description, Figure 3-14 shows an example of a simple instruction memory interface. In this example, the external instruction memory has a capacity of 32K words, and the read/write timing without wait control and 1-wait read timing are shown.
Figure 3-14. Example of External Instruction Memory Interface
PD77016
ID0-ID31 IA0-IA15 PWR SRAM (4 x 32K words x 8 bits) D0-D7 A0-A14 OE WR CS
CLKOUT IA0-IA15
ID0-ID31 PWR No wait read (IWTR=0x0000) 1 internal wait cycle read (IWTR=0x0054) No wait write (IWTR=0x0000)
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(2) Stack (STK) and stack pointer (SP)
Stack (STK) is a register file dedicated to saving/restoring PC and consists of 16 bits by 15 levels. It is used to: * Save return address when a subroutine is called * Save the current address under execution when an interrupt occurs For the details of the interrupt, refer to section 3.4.4 "Interrupt." A pointer register that points to the stack level (called stack top) that is currently to be accessed is called stack pointer (SP). SP consists of 16 bits, but setting a value other than 0 to 15 to this pointer is prohibited. The stack top and SP are connected to the main bus; therefore, data can be exchanged with a general-purpose register via the main bus. When the stack overflows or underflows, stack error flag (ste) of ESR is set to 1.
Remark Do not write the RET or RETI instruction just after the inter-register transfer instruction to load from/ store to STK or SP.
(3) Related instructions
The operations of the program counter (PC), stack (STK), and stack pointer (SP) can be viewed from the following two points: * Instruction execution and PC operation * Branch instruction and operations of PC, SP, and STK (a) Instruction execution and PC (normal operation) The value of PC is incremented each time an instruction is fetched. Figure 3-15 shows the image when this PC operation is combined with pipeline execution.
Figure 3-15. Normal Operation of PC
Time PC
Instruction sequence
n F1
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 D1 F2 E1 D2 F3 E2 D3 F4 E3 D4 E4
Instruction 1 (address n) Instruction 2 (address n + 1) Instruction 3 (address n + 2) Instruction 4 (address n + 3)
Remarks Fn: fetch cycle of instruction n Dn: decode cycle of instruction n En: execution cycle of instruction n
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(b) Branch instruction and operations of PC, SP, and STK The branch instructions are classified into the following three types: <1> Jump and subroutine call The branch instructions are further subdivided into these two types of instructions, depending on whether the address of the instruction under opcode fetch (value of the PC) is saved to the stack or not. * JMP instruction Does not save the address of the instruction under opcode fetch to the stack. Therefore, program flow cannot automatically return to the branch source address from the branch destination address. * Subroutine call instruction : Saves the address of the instruction under opcode fetch (address of the instruction next to the subroutine call instruction) to the stack. To return program flow from the branch destination address to the branch source address, the return instruction is used. <2> Branch viewed from PC setting format The branch instructions can be classified into the following two types when viewed from the format in which the branch destination address is set to the PC: * Immediate jump/call This format is called immediate jump or immediate call. The JMP/CALL instructions for which a numeric value is coded as an operand execute branch in this format. At this time, the numeric value is added to or subtracted from the current PC value as 16-bit 2's complement. Therefore this is in fact a relative branch, relative to the current PC value. Program flow can be branched in the range of 32K words, i.e., in the entire 64K-word space.
Caution
When this instruction is written in assembler, write a direct branch destination address or label as the operand. The assembler calculates the correct relative branch distance to the current PC value automatically.
* Register indirect jump/call This format is called register indirect jump or register indirect call. The JMP/CALL instructions for which DPn register is described as an operand execute branch in this format. At this time, the value of the DPn register is directly set to the PC.
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<3> Conditional or unconditional branch The PD7701x family does not have dedicated conditional branch or conditional return instructions. Conditional branch is realized by combining conditional instructions and branch instructions, and conditional return is realized by combining conditional instructions and return instructions. These are classified into the following two types: * Unconditional JMP/CALL/RET instructions These instructions always (unconditionally) branch (JMP/CALL/RETurn). * Conditional JMP/CALL/RET instructions These instructions branch (JMP/CALL/RETurn) only when the condition of the combined conditional instructions is true. Table 3-15 summarizes the above discussion. Note that, although the processing execution sequence when branch takes place does not differ depending on whether the instruction is conditional or unconditional, the actual execution time is 1 instruction cycle longer when a conditional instruction is used in combination. Although this is not indicated in the table, if the condition of a conditional branch instruction is not satisfied, delay due to pipeline hazard does not occur (refer to Figures 3-16 to 3-19).
Table 3-15. Classification of Branch Instructions
Instruction name Condition judgment Jump instruction Unconditional Conditional Unconditional Conditional Subroutine call instruction Unconditional Conditional Indirect subroutine call instruction Unconditional Conditional Return instruction Unconditional Conditional Interrupt return instruction Unconditional Conditional -- 1 -- 1 2 3 2 3 Register indirect absolute 1 PC relative 1 2 3 3 Register indirect absolute 1 PC relative Address specification Word length 1 Instruction cycles 2 3 3
Caution
Above number of instruction cycles are valid if the condition is satisfied and program flow branches. If the condition is not satisfied, even the conditional branch occupies one instruction cycle because the branch is not performed and no pipeline hazard occurs.
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Figures 3-16 to 3-19 show the timing of the following instructions: * Unconditional immediate jump * Unconditional indirect jump * Conditional immediate jump (condition satisfied: jump) * Conditional immediate jump (condition not satisfied: pass) The meanings of the symbols in each figure are as follows (n=0,1,2,..):
ifn idn ia p pop popi : : : : : : instruction fetch instruction decode instruction address operation purge stack pop interrupt pop jifn exn addr push jdec : : : : : jump destination instruction fetch instruction execution address output stack push jump destination decode
Figure 3-16. Timing of Unconditional Immediate Jump
Clock JMP instruction if1 id1 ia addr
Next instruction
if2
nop
--
Instruction at JMP destination
jif3
id3
ex3
Next instruction
jif4
id4
ex4
Figure 3-17. Timing of Unconditional Indirect Jump
Clock JMP instruction if1 id1 ex1 addr
Next instruction
if2
nop
--
Next instruction Instruction at JMP destination
if3
nop
--
jif4
id4
ex4
Next instruction
jif5
id5
ex5
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Figure 3-18. Timing of Conditional Immediate Jump (condition satisfied: branch)
Clock Conditional JMP instruction if1 id1 ia idec addr
Next instruction
if2
nop
--
Next instruction Instruction at JMP destination
if3
nop
--
jif4
id4
ex4
Next instruction
jif5
id5
ex5
Figure 3-19. Timing of Conditional Immediate Jump (condition not satisfied: pass)
Clock Conditional JMP instruction Next instruction if1 id1 idec
if2
id2
ex2
Next instruction Next instruction
if3
id3
ex3
if4
id4
ex4
Next instruction
if5
id5
ex5
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(c) Operation of subroutine call/return Subroutine call is executed by the CALL instruction. When the CALL instruction is executed, execution branches in the following procedure: 1. The value of SP is incremented (pre-increment). 2. The value of PC (address next to the CALL instruction) is saved to the STK indicated by SP. 3. The branch destination address is set to the PC. At this time, if the branch destination is given as a numeric value, the numeric value is added to or subtracted from the current PC value as 2's complement. If the branch destination is given by the DPn register, the value of the DPn register is directly set to the PC.
To return execution from a subroutine, the RET instruction is used. This instruction is executed in the following procedure: 1. The value in the STK indicated by the SP is restored to the PC. 2. The value of SP is decremented (post-decrement).
Remark For the timing of the CALL instruction, refer to the timing of the JMP instruction. The timing of the CALL instruction is the same as that of the JMP instruction, except that the return address is saved to the stack. The timing of the return instruction is the same as that of the immediate jump instruction, i.e. it takes two instruction cycles.
(d) Operation when interrupt occurs When an interrupt occurs, the address of the instruction under opcode fetch (address of the instruction when the interrupt is acknowledged) is saved to the stack, and the branch destination address is set to the PC. To return from the interrupt, the RETI (return from Interrupt) instruction is used. For the operation of the interrupt, refer to section 3.4.4 "Interrupt."
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3.4.3 Flow control block
In general, a high-level language provides sophisticated flow control syntax (e.g., for loop and while loop of the C language). The PD7701x family is provided with hardware that allows this flow control to be directly described as assembly instructions, and performs loop/ repeat operation without any timing overhead. The loop/repeat control circuit controls the loop/repeat operations. Flow control is managed by the following registers and functional blocks: * Repeat counter (RC) This 16-bit counter register holds the number of repetitions of a repeat instruction. * Loop start address register (LSA) This 16-bit register holds the loop start address during loop execution. * Loop end address register (LEA) This 16-bit register holds the loop end address during loop execution. * Loop counter (LC) An initial value is set to this 16-bit register when execution of the LOOP instruction is started. Each time loop is executed once, the value of this register is decremented. When the current value of the register reaches 0, it indicates the end of the loop. * Loop stack (LSTK) The LSTK is a register file with 3 x 16 bits x 4 levels to save and store the LSA, LEA and LC values. It saves the LSA, LEA and LC values by the loop instruction. The values are restored to the LSA, LEA and LC upon loop termination or by the loop pop instruction. This file serves as one of the following three 16-bit registers for input/output to/from the main bus with inter-register transfer instruction. * LSR1: Saves/restores loop start address (stack for LSA) * LSR2: Saves/restores loop end address (stack for LEA) * LSR3: Saves/restores loop counter (stack for LC) If LSR1 is specified for the inter-register transfer instruction source, the LSP is decremented after transfer. If LSR1 is specified for the inter-register transfer instruction destination, data is transferred after the LSP is incremented. [Software loop stack] If a loop over 4 levels causes a loop stack overflow, the return address is lost and processing cannot return normally. When you know in advance that there is a loop over 4 levels, the contents of the stack should be saved to memory prior to stack overflow, so that a normal return can be executed even though another loop operation is performed. This method is called software loop stack. In this case, note that the contents stored should be rewritten to the loop stack in correspondence with stack level, when stack contents are saved to memory. A software loop stack programming example is shown below.
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Software loop stack example: * Push (DP0: Save address) R0L = *DP0- - R0L = LSR3; *DP0- - = R0L; R0L = LSR2; *DP0- - = R0L; R0L = LSR1; *DP0- - = R0L; * Pop (DP0: Restore address) R0L = *DP0++; LSR1 = R0L; R0L = *DP0++; LSR2 = R0L; R0L = *DP0++; LSR3 = R0L;
* Loop stack pointer (LSP) This pointer indicates the current position of LSTK. Although this is a 16-bit register, the value that can be set to it is 0 to 4. The LSP value can be input/output to/from the main bus with inter-register transfer instruction. The LSP value becomes 0 by reset. The LSP is incremented/decremented by 3 bits (bits 2 to 0). Bits 15 to 3 are fixed to 0. The LSP is incremented in the following cases: * When the LSA, LEA, and LC values are saved to the LSTK by the loop instruction * When the LSR1 is specified for the inter-register transfer instruction destination The LSP is decremented in the following cases: * When the LSTK value is returned to the LSA, LEA, and LC upon loop termination or by the loop pop instruction * When LSR1 is specified for the inter-register transfer instruction source
Cautions 1. When the value of LSP is not between 0 to 4, a stack overflow or underflow occured indicating an error. 2. Do not set the LSP value between 5 and 0xFFFF.
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* Loop/repeat controller (LRC) This circuit controls the loop and repeat instructions.
Caution
All the above registers, except RC, are connected to the main bus, so that data can be transferred between them and general-purpose registers.
Flow control has the following two functions: * Repeat function (REP instruction) * Loop function (LOOP instruction, LPOP instruction)
(1) Repeat function
The repeat function that is written by the REP instruction realizes repetition of one instruction on a count basis. The instruction to be repeated the repeat target instruction, follows immediately the REP instruction itself. (a) Format of repeat counter (RC) Figure 3-20 shows the format of the repeat counter (RC).
Figure 3-20. Format of RC
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RF
Count value setting field Setting range: 1 to 32767 Repeat flag (RF): automatically controlled by the repeat controller. RF=0: repeat in progress RF=1: end of repeat (not in progress)
Caution
During the entire repeat operation no interrupt will be acknowledged. For further details refer to section 3.4.4 "Interrupts".
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(b) Summary of repeat function The repeat function can be summarized as follows: * A single instruction is repeated. * The number of repetitions can be directly given as a numeric value or by using a general-purpose register (R0L-R7L). * The number of repetitions ranges from 1 to 32767. * The value of PC is not incremented during repeat operation. * RC is decremented each time the instruction is repeated, and repeat ends when the instruction has been repeated the specified number of times. * The repeat function depends on RC only, and is not counted as nesting of loop instructions.
(c) Procedure of repeat function execution When the REP instruction is executed, the repeat function is implemented in the following procedure. 1. The number of repetitions given as the parameter of the REP instruction is set to RC. 2. The value of PC is incremented, and the instruction immediately after the REP instruction is repeated. At this time, an invalid cycle of one instruction cycle is generated. 3. During repeat operation, PC holds a next address of this instruction that has been repeated. 4. The value of RC is decremented each time the instruction has been repeated once. After the instruction has been repeated the specified number of times, repeat ends. 5. When repeat ends, the value of PC is incremented. When execution shifts from the instruction that has been repeated to the next instruction, the pipeline stages are successive. Therefore, no overhead occurs when repeat ends.
For the repeat instruction, refer to "PD7701x Family User's Manual Instructions".
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(d) Repeat execution timing The following figures show an example in which the REP instruction is repeated two times. Figure 3-21 shows the assembly program, and Figure 3-22 shows the execution timing.
Figure 3-21. Example of Repeat Instruction (repetition of 2 times)
REP R0 /= 2; R1;
Figure 3-22. Repeat Execution Timing (repetition of 2 times)
Clock
Repeat instruction
if1
id1
RC RF
RF RC
1 x
1 x
0 2 RC--
0 1 RC--
1 0
1 0
Updating instruction register and program counter is stopped at this time. Instruction to be repeated Instruction to be repeated Instruction to be repeated Instruction next to one to be repeated Next instruction if2 nop --
if2
id2
ex2
if2
id2
ex2
if3
id3
ex3
if4
id4
ex4
Updates program counter instruction register
Remarks RF: repeat flag
RC: repeat counter
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(2) Loop function
The loop function that is described by using the LOOP instruction realizes loop flow of an instruction group consisting of 2 to 255 instructions on a count basis. Nesting of loop is supported by a four level hardware loop stack. To escape from the loop at any point, the LPOP instruction is provided, so that flexible loop control is performed. (a) Format of loop counter (LC) Figure 3-23 shows the format of the loop counter (LC).
Figure 3-23. Format of LC
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LF
Count value setting field Setting range: 1 to 32767 Loop flag (LF): automatically controlled by the loop controller. LF=0: loop in progress LF=1: end of loop (not in progress)
Remark The loop flag LC is also contained in the status register (SR) (refer to section 3.4.4 "Interrupt").
(b) Summary of loop function The loop function can be summarized as follows: * Groups 2 to 255 instructions as a loop element. * The number of loops can be given directly by a numeric value or by using a general-purpose register (R0L-R7L). * The number of loops ranges from 1 to 32767. * Nesting of up to 4 levels can be realized by the loop stack. * Execution can be escaped from the loop when: (1) The count value reaches 1 (2) The LPOP instruction and then JMP instruction are executed
Remark For interrupt processing in conjunction with loop operations (refer to section 3.4.4 "Interrupt").
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(c) Loop function execution procedure When the LOOP instruction is executed, the loop function is implemented in the following procedure: <1> When loop is started 1. The value of LSP is incremented (pre-increment). 2. The current LSA, LEA, and LC are saved to LSTK indicated by LSP. 3. The loop start address is set to LSA. 4. The loop end address is calculated and set to LEA. 5. The number of loops is set to LC.
<2> During loop operation 1. The value of LC is decremented if the values of PC and LEA are equal. 2. The value of LSA is set to PC if LC is not 1. If LC is 1, the loop end processing is executed.
<3> Loop end processing 1. The value of PC is incremented. 2. The value of LSTK indicated by LSP is restored to LSA, LEA, and LC. 3. The value of LSP is decremented (post-decrement).
<4> Loop end processing by LPOP instruction The LPOP instruction discards one level of loop by performing the following processing. 1. Restores the value of LSTK indicated by LSP to LSA, LEA, and LC. 2. Decrements the value of LSP (post-decrement). For the LOOP and LPOP instructions, refer to "PD7701x Family User's Manual Instructions".
Caution
The LPOP instruction does not automatically control PC for escaping from the loop. Therefore, execute the LPOP instruction after escaping from the loop by using the JMP instruction, or execute the LPOP instruction and then escape from the loop by using the JMP instruction (Refer to "PD7701x Family User's Manual Instructions").
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(d) Timing of loop execution (example of two loops operation) Figure 3-24 shows an example of the LOOP instruction execution timing. In this example, two loops operation in which a group of two instructions is executed only once is performed.
Figure 3-24. Loop Execution Timing (example of 2 loops operation)
Clock Loop instruction
if1
id1
+Isp push lea= set 1 x 0 2 0 2 LC0 1 pop 0 0 1 0 1 0 1 0
LF LC
1 x
First instruction in loop First instruction in loop (1st fetch) Second instruction in loop (1st fetch) First instruction in loop (2nd fetch) Second instruction in loop (2nd fetch) First instruction after loop Remarks
if2
nop Loop escape address if2 id2 ex2
if3
id3
ex3
if2
id2
ex2
if3
id3
ex3
if4 LF: loop flag LC: loop counter
id4
ex4
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3.4.4 Interrupt
The PD7701x family has powerful interrupt functions. This section describes the following functions: * Interrupt cause * Interrupt control function * Interrupt acknowledgment condition * Hardware condition of external interrupt * Interrupt vector
(1) Interrupt cause
There is a total of 10 interrupt causes available including internal and external interrupts. * Internal interrupt : Caused by events specified by internal peripherals. Six internal causes are available. * External interrupt: Triggered by external causes via hardware signal pins. Four external causes are available. Table 3-16 lists all the interrupt causes.
Table 3-16. Interrupt Causes
Internal/external Internal Interrupt cause SI1 input Completion of serial interface #1 input SO1 output Enabling output of serial interface #1 SI2 input Completion of serial interface #2 input SO2 output Enabling output of serial interface #2 HI input Completion of host interface input HO output Enabling output of host interface External INT1 Falling edge of external signal pin INT1 INT2 Falling edge of external signal pin INT2 INT3 Falling edge of external signal pin INT3 INT4 Falling edge of external signal pin INT4
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(2) Interrupt control function
All interrupt causes, regardless of whether they are internal or external, are handled as independent events and at independent levels. Here is the summary of the functions to control the interrupts: * Each interrupt cause can be enabled or disabled independently. * All interrupts can be enabled or disabled as one group (global enable). * A stack for global interrupt enable function is provided, so that multiple (nesting of) interrupts can be handled. * The interrupt vectors (entry points of interrupt servicing routine at interrupt acknowledgement) for all interrupt causes are fixed. * When an interrupt has been acknowledged, the current instruction is aborted, and program execution control is transferred to the specified entry point. * After the interrupt servicing routine is executed completely, control is returned to the instruction that was suspended by the interrupt. * When an interrupt request is issued during the execution of Jump or some other instructions, a delay cycle is inserted before the interrupt is acknowledged.
(3) Interrupt acknowledgment condition
When an interrupt request is generated by an interrupt cause, the interrupt will be acknowledged if both following conditions are satisfied: * Global interrupt enable (EI) flag value is 0 (enable). * Interrupt cause enable flag value corresponding to the requested interrupt is 0 (enable). Note, however, that acknowledging the interrupt is delayed in any of the following cases: * While a jump instruction is fetched, decoded, or executed * While a repeat instruction or a repeat target instruction is fetched, decoded, or executed * While a loop instruction is fetched, decoded, or executed * While a loop termination instruction (instruction at loop end address) is fetched
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(4) Hardware conditions of external interrupt
External interrupts (INT1-INT4) are acknowledged when the falling edges of the corresponding pins have been detected. To issue several interrupt requests successively, make the corresponding pin to high and then to low, for each interrupt request, to create a falling edge. Note that each of the high and low levels must have enough duration for the system to recognize level changes. Figure 3-25 shows external interrupt timing.
Figure 3-25. External Interrupt Timing
CLKOUT tw(INTL) INT1-INT4
IA0-IA15
Interrupt vector
Caution
In case of the PD77015, 77017, 77018, 77018A, and 77019, if the processor is in HALT mode, the active (low) time of an external interrupt INT1-INT4 has to be extended to minimum 8xtw(INTL), since the CLKOUT period during HALT mode is extended to 8 times longer.
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(5) Interrupt vector
Every interrupt cause has a dedicated entry point (also called vector). These vectors for interrupt causes are sequentially set from the start position (address 0x200) of the internal instruction area, creating a 64-word table. Each cause is assigned four instruction addresses. If interrupt servicing is not completed within four instructions including the interrupt return instruction (RETI), execution must branch beyond address 0x240 for service completion. (a) Interrupt vector table Table 3-17 shows the interrupt vector table.
Table 3-17. Interrupt Vector Table
Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C Internal/external Internal -- -- -- External External External External Internal Internal Internal Internal Internal Internal -- -- Interrupt cause Reset Reserved Reserved Reserved INT1 INT2 INT3 INT4 SI1 input SO1 output SI2 input SO2 output HI input HO output Reserved Reserved
Cautions 1. Although the reset signal is not an interrupt, it is treated as a vector entry as if it is an interrupt. 2. It is recommended that the vector of unused interrupt causes be branched to an abnormality processing routine. 3. Because the vector area of the mask ROM model also exists in the internal RAM area, this area must be booted up. Also because the entry after reset is address 0x200, booting up address 0x200 is necessary even when the internal instruction RAM and interrupts are not used.
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(b) Example of processing of interrupt vector See the following example.
; Definitions #define SI1 0x3800 #define SO1 0x3800 ; address of serial input register ; address of serial output register
; Interrupt vector table int_vec imseg at 0x200 ; start of vector table : : org 0x220 (0x220) (0x221) (0x222) (0x223) JMP INPUT NOP NOP NOP ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; serial input #1 interrupt vector branches to application area for more than 4 instructions
(0x224) (0x225) (0x226) (0x227)
R0H=*DP4++ *SO1:y=R0H RETI NOP
serial output #1 interrupt vector interrupt service less than 4 instructions fetch data from y-memory transter it to serial output #1 return from interrupt serial input #2 interrupt serial input #2 is not used (RETI instruction cannot be written at brginning of vector)
(0x228) NOP (0x229) RETI (0x22A) NOP (0x22B) NOP : : ; Main program segment ; main imseg ; : : INPUT: R0H=*SI1:y R1=*DP0 R1=R1+R0H*R2H *DP0=R1H RETI
start at 0x240 (automatically located to 0x240 by the Linker)
; serial input #1 interrupt servicing routine ; fetch data from serial input #1 ; ; ; ; return from interrupt
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(6) Interrupt control software
Interrupts are controlled by the following registers (refer to Figure 3-9 "Program Control Unit"): * Status register (SR) * Interrupt enable flag stack register (EIR) (a) Status register (SR) This is a 16-bit register that enables or disables all the interrupts (general interrupt enable/ disable), and enables or disables each interrupt cause separately. When the value of a bit of this register is 0, the corresponding interrupt is enabled; when the bit is 1, the interrupt is disabled. The values of SR can be read and written by executing the register-to-register transfer instruction. This register is set to 0xF000 at reset.
Interrupt enable flag EI 15 EP 14 EB 13 LF ho 12 11 10 9 Reserved Interrupt enable flag for each cause On-chip I/O device hi 8 so2 7 si2 6 so1 5 si1 4 External interrupt master int4 3 int3 2 int2 1 int1 0
<1> Interrupt enable flags (EI: enable interrupt, EP: enable interrupt previous, EB: enable interrupt before) The EI, EP, and EB flags enable or disable all the interrupts. When the value of these flags is 0, the interrupts are enabled; when it is 1, the interrupts are disabled. These three flags, EI (enable interrupt), EP (enable interrupt previous), and EB (enable interrupt before), enable or disable the current interrupts, and interrupts one levels before and two levels before. These flags are the same as the EI, EP, EB flags at bits 15-13 of the EIR register (refer to section (b) "Interrupt enable flag stack register"). Therefore, the values of bits 15-13 of the SR are always the same as those of the EIR register. The following nesting of interrupt and stack manipulation are handled by the EI, EP, and EB flags and E3 through E15 flags of the EIR register (refer to section (b) "Interrupt enable flag stack register"). When interrupt has been acknowledged; value of EB --> E3 of EIR register value of EP --> shifted to EB value of EI --> shifted to EP EI --> set to 1 (all interrupt disable) Vice versa at RETI instruction; value of EI --> wasted value of EP --> shifted to EI value of EB --> shifted to EP value of E3 of EIR register --> EB
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For multiple interrupts, refer to section (b) "Interrupt enable flag stack register". The interrupt flag before updating is valid while a transfer instruction which specifies SR as the destination is fetched and executed, that is, between the transfer instruction and the next instruction, and between the next instruction and the instruction that follows.
Example of changing interrupt enable flag (enabled --> disabled)
Initial status:EI=0; (interrupt enabled) R0L=EIR; R0=R0|0x8000; EIR=R0L; Next instruction; May branch to interrupt servicing Instruction that follows;
Caution
To rewrite the EP and EB flag, be sure to disable all the interrupts (EI = 1).
<2> Loop flag (LF) This flag indicates whether execution is in a loop or not. The value "0" shows that the execution is in a loop, and "1" for not in a loop.
Caution
Do not change this flag when modifying any interrupt mask flags. Modify interrupt mask flags always by reading the current SR contents and mask only the dedicted flags (refer to following examples).
<3> Reserved flags A write to these flags is ignored. Undefined values are returned when these flags are read.
<4> Interrupt enable flags for each cause These flags enable or disable the corresponding interrupt causes. When the value of any of these flags is 0, the corresponding interrupt is enabled; when it is 1, the interrupt is disabled. The values of these flags are not affected even when the respective interrupts have been acknowledged. There are the following five types of these flags, totaling 10. * External interrupts 1-4 : Interrupts from external interrupt pins (INT1-INT4). * SI1, SI2 : Interrupts that occur when serial input has been completed and data has been received by the serial data register (SDT: for input).
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* SO1, SO2 : Interrupts that occur when serial output has been completed and transmit data can be written to the serial data register (SDT: for output). * HI * HO : Interrupt that occurs when host interface input has been completed and data has been received by the host data register (HDT: for reception). : Interrupt that occurs when host interface output has been completed and transmit data can be written to the host data register (HDT: for transmission).
Caution
To rewrite any of the above flags, be sure to disable all interrupts (EI = 1).
Example of rewriting interrupt enable flag for each cause (enabled --> disabled)
R0L=EIR R0=R0|0x8000 EIR=R0L NOP R0L=SR R0=R0|0x0001 SR=R0L
; ; ; ; ; ; ;
disable interrupts generally here: via EIR register set EI = 1 (general interrupt disabled) write back to EIR wait until interrupt disable becomes valid disable external INT1 via SR register set INT1 = 1 (disabled) write back to SR
(b) Interrupt enable flag stack register (EIR) This 16-bit register stacks the general interrupt enable flags. When a bit of this register is 0, the corresponding interrupt is enabled; when the bit is 1, the interrupt is disabled. The values of EIR can be read and written by executing the register-to-register transfer instruction. The value of this register is set to 0xFFFF at reset.
15 EI 14 EP 13 EB 12 E3 11 E4 10 E5 9 E6 8 E7 7 E8 6 E9 5 4 3 2 1 0
E10 E11 E12 E13 E14 E15
When an interrupt has been acknowledged, the contents of this register are shifted 1 bit to the right, and the bit EI is set to 1 to disable all interrupts generally. The register contents are shifted 1 bit to the left by execution of the interrupt return instruction RETI where E15 is set to 1 simultaneously. Cause of them, multiple interrupts of up to 16 levels are guaranteed. Bits 15-13 (EI, EP, EB) are the same as the bits 15-13 of the SR register. The interrupt enable/disable status can be changed by writing EIR with the register-toregister transfer instruction. However, note that this change will be valid three instructions after writing EIR.
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Example of enabling interrupt (disabled status --> enabled)
Initial status:EI=1 (interrupt disabled) R0L=EIR; R0=R0&0x7FFF; EIR=R0L; Instruction 1; Instruction 2; Instruction 3;
Interrupt disabled during this period Interrupt enabled
<1> EIR and multiple interrupts As described earlier, a multiple interrupt system can be configured by using the EIR register. This paragraph describes the concept of multiple interrupts, taking an example shown in Figure 3-26 and focusing on EIR. [Prerequisite] All interrupts are enabled by the corresponding interrupt enable flags. [Process]
(1) Clear the EI bit to 0 to enable all interrupts. (2) INT1 is acknowledged, and control is transferred to the INT1 servicing routine. At this time, the contents of the EIR register are shifted 1 bit to the right, and one level of interrupt status is stacked. At the same time, bit 15 (EI) is set to 1, disabling the other interrupts. (3) The interrupts are enabled (EI=0) in the INT1 servicing routine. (4) INT2 is acknowledged, and control is transferred to the INT2 servicing routine. In the same manner as before, the contents of EIR are shifted 1 bit to the right, and EI is set to 1, disabling the interrupts. (5) INT3 request is generated while the INT2 servicing routine is executed. However, this interrupt is not acknowledged because it is disabled, but recorded. (6) When the INT2 servicing routine is ended in the RETI instruction, the contents of EIR are shifted 1 bit to the left. Consequently, the status before acknowledging the INT2 interrupt is restored. In this status, EI=0, enabling the interrupts. (7) The recorded INT3 is now acknowledged, and control is transferred to the INT3 servicing routine. The contents of EIR are shifted 1 bit to the right again, and EI is set to 1. If necessary, clear EI to 0. (8) When the INT3 servicing routine is ended in the RETI instruction, the contents of EIR are shifted 1 bit to the left, and the status before INT3 was acknowledged is restored (INT1 is being processed). (9) Execution of the INT1 servicing routine continues. When the RETI instruction is executed at the end of this routine, the status before INT1 was acknowledged is restored.
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Figure 3-26. Multiple Interrupt Processings
Main program Interruption is allowed
EI=0
EIR=0111...
INT1 servicing routine EIR=0011... EI=0 EIR=1011... INT1 EIR=1001... INT2 EIR=0111... RETI
Interruption is not allowed INT2 servicing routine
Interruption is allowed INT3 RETI EIR=0011... INT3 servicing routine EI=0 EIR=0001...
EIR=1001...
EIR=0011...
RETI
<2> Differences between SR and EIR The most significant three bits of the SR and EIR registers (EI, EP, and EB) are accessed as common bits. The EI bit directly enables or disables the current interrupt, and therefore care must be exercised in manipulating this bit. The differences between SR and EIR are as follows, when the EI bit is manipulated: * To enable the interrupts, the EI bit of either the SR or EIR register can be used. * To disable the interrupts, use of the EI bit of the EIR register is recommended. There is no problem when the interrupts are enabled by the EI bit because the interrupts have been disabled up to that point. When the interrupts are disabled, however, the following situation may arise:
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R0L=SR
; disable interrupt generally here:
via SR register
<- Interrupt occurs and jump to interrupt servicing routine: ; Interrupt servicing routine ; This routine disables INT1 interrupt individually ; R1L=SR ; set INT1=1 (disabled) R1=R1|0x0001 ; write back to SR SR=R1L ; return from interrupt RETI <- SR has changed meanwhile R0=R0|0x8000 SR=R0L : : ; set EI=1 ; write back to SR
In this case, writing data to the SR register is ignored while the interrupt is serviced. To avoid this situation, it is recommended to use the EI bit of the EIR register, rather than that of the SR register, to disable the interrupts.
(7) Interrupt sequence
(a) Acknowledging an interrupt When an interrupt has been acknowledged, the following operations are performed: * An instruction that was fetched immediately before the interrupt has been acknowledged is kept pending. * The EIR register is shifted 1 bit to the right to stack 1 level. * The EI bit is set to 1 to disable the interrupts. * SP is incremented. * The address of the pending instruction is saved to STK specified by SP. * A specified interrupt vector address is set to PC, and execution branches to interrupt servicing routine. Figure 3-27 shows timing of acknowledging an interrupt.
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Figure 3-27. Interrupt Acknowledging Timing
Clock INT Interrupt request signal Interrupt servicing Synchro- Synchro- Interrupt Interrupt Fetch nization nization request judgment save data
Interrupt disabled EI: disable Purged and no execution

if1 id1 ex1
Instr #1 Interrupt servicing instruction #1 Interrupt servicing instruction #2
iif1
iid1
iex1
iif2
iid2
iex2
Remarks ifn : instruction fetch idn : instruction decode exn: instruction execution
iifn : interrupt instruction fetch iidn : interrupt instruction decode iexn: interrupt instruction execution
(b) Returning from interrupt When the RETI instruction (interrupt return) is executed, the following are processed in two to three instruction cycles, and execution returns from the interrupt servicing routine. * The value of STK indicated by SP is restored to PC. * SP is decremented. * The EIR register is shifted to the left, and interrupt enable flags are restored. * Execution branches to the return address (the instruction that was kept pending when the interrupt was acknowledged). Figure 3-28 (a) and (b) shows the return timings by using an unconditional RETI instruction and a conditional RETI instruction with the condition satisfied, respectively.
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Figure 3-28. Timing by RETI Instruction (a) Unconditional
Clock Interrupt acknowledge delay signal RETI if1 id1 popi addr Instruction of address next to RETI Instruction next to one at which interrupt was acknowledged if2 nop --
rif1
rid1
rex1
ifn : instruction fetch idn: instruction decode rifn : interrupt return destination instruction fetch ridn : interrupt return destination instruction decode rexn: interrupt return destination instruction execution
(b) Conditional instruction: Condition satisfied
Clock Interrupt acknowledge delay signal RETI if1 id1 jdec popi addr Instruction of address next to RETI Instruction at address next to that of RETI + 1 Instruction next to one at which interrupt was acknowledged
if2
nop
--
if3
nop
--
rif1
rid1
rex1
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(8) Delaying interrupt acknowledgment
In the course of acknowledging an interrupt, registers SP, STK, and PC are automatically managed. To prevent conflicts with instructions that address these registers, acknowledging an interrupt is delayed when any of the following instructions that may cause such a conflict is executed. Note that the interrupt acknowledgement itself (branching to the interrupt servicing routine) still introduces only a single delay cycle.
Caution
Interrupt is not acknowledged under following conditions and interrupt request is held until interrupt enables; * During peripheral I/O wait function * During external memory access wait cycles * During repeat process
(a) Instructions generating delay of one instruction cycle The following instructions cause a delay of interrupt acknowledgment of one instruction cycle: * Decoding of unconditional JMP instruction (PC-relative jump by immediate data) * Decoding of unconditional CALL instruction (PC-relative jump by immediate data) * Decoding of unconditional RET instruction * Decoding of unconditional RETI instruction * Decoding of FINT instruction * Fetching of loop end instruction Figure 3-29 illustrates how an interrupt is delayed that occurs during the processing of any of these instructions.
Figure 3-29. Interrupt Delay Timing (one-cycle delay)
Clock
Interrupt acknowledgment delay signal JMP instruction if1 id1 ia Instruction at address next to that of JMP instruction First instruction at branch destination (Interrupt) First instruction in interrupt routine iif1 iid1 iex1 addr Fetching the first instruction of the interrupt servicing routine is prevented in this cycle. nop --
if2
jif1
nop
--
Remarks jifn, jidn, jexn: fetch, decode, or execution of instruction at branch destination
iifn, iidn, iexn: fetch, decode, or execution of interrupt routine ia: branch destination address calculation addr: address
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(b) Instructions generating delay of two instruction cycles The following instructions cause a delay of interrupt acknowledgment of two instruction cycles: * Decoding of onditional JMP instruction (PC-relative jump by immediate data) * Decoding of conditional CALL instruction (PC-relative jump by immediate data) * Decoding of conditional RET instruction * Decoding of conditional RETI instruction * Decoding of unconditional/conditional register-indirect JMP instruction * Decoding of unconditional/conditional register-indirect CALL instruction * Decoding of REP instruction * Decoding of LOOP instruction Figure 3-30 illustrates how an interrupt is delayed that occurs during the execution of any of these instructions.
Figure 3-30. Interrupt Delay Timing (two-cycle delay)
Clock
Interrupt acknowledgment delay signal Conditional JMP instruction if1 id1 ia
Instruction at address next to that of conditional JMP instruction Instruction at address next to that of conditional JMP instruction + 1
ex1
addr Fetching the first instruction of the interrupt servicing routine is prevented in between these cycles.
if2
nop
--
if3
nop
--
First instruction at branch destination (Interrupt) First instruction in interrupt routine
jif1
nop
--
iif1
iid1
iex1
Remarks
ifn: fetch of instruction n idn: decode of instruction n exn: execution of instruction n jifn, jidn, jexn: fetch, decode, or execution of instruction at branch destination iifn, iidn, iexn: fetch, decode, or execution of interrupt routine ia: branch destination address calculation addr: address
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(9) Conflict and recording of interrupt
(a) Recording interrupt When an interrupt has been acknowledged, an interrupt servicing program is executed. During the execution, the global interrupt enable flag "EI" is automatically set to 1 (disable). Therefore, if another interrupt occurs during this period, it is not acknowledged immediately, but is recorded classified by the cause. When the interrupt servicing program has been ended in the RETI (return from interrupt) instruction, the EI flag is cleared to 0, enabling other interrupts. Consequently, the recorded interrupt is acknowledged and processed. This interrupt recording function works not only when EI is 1, but also when the corresponding interrupt enable flags are set to the disable state.
Cautions 1. All interrupt request are recorded, disregarding the settings of all interrupt enable/disable flags. 2. Only one level of interrupt can be recorded per cause. 3. The internal flag that records the occurrence of an interrupt is not cleared unless the corresponding interrupt is acknowledged. 4. The FINT instruction discards all interrupt requests. For further details refer to PD7701x Family User's Manual Instructions.
(b) Priority of interrupt It is undefined which interrupt is served first if two or more interrupts occur at the same time.
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3.4.5 Error status register (ESR)
This 16-bit register holds error flags which indicate some error status's of the processor. A write to bits 15-4 of this register is ignored. Undefined values are returned when these flags are read. Bits 3-0 of ESR are set to 1 when an error occurs. The values of these bits are not clear to 0 unless a hardware reset is applied or they are rewritten by program (inter-register instruction). The values of ESR can be read and written by executing the inter-register transfer instruction. The value of this register is cleared to 0 at reset.
15 ESR 14 13 12 11 10 9 8 7 6 5 4 3 ovf 2 ste 1 lse 0 bac
(a) ovf: Overflow error flag This flag is set to 1 if an overflow occurs while the operation unit calculates data in the 40-bit two's complement format. (b) ste: Stack error flag This flag is set to 1 when the stack overflows or underflows. (c) lse: Loop stack error flag This flag is set to 1 when the loop stack overflows or underflows. (d) bac: Bus access error flag This flag is set to 1 when prohibited parallel data memory access combination is executed. Combinations of prohibited parallel data memory access are as follows; * Internal ROM and Internal ROM * Internal ROM and External area * External area and External area * Peripheral area and Peripheral area
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3.5
Data Addressing Unit
Generally, a DSP is required to access a large quantity of data flexibly and efficiently. The PD7701x family is provided with dedicated data addressing units to efficiently access the data memory spaces.
3.5.1 Block configuration
Figure 3-31 is the block diagram of the data address unit.
Figure 3-31. Data Addressing Unit
Immediate value
16 16 16
16
16
Immediate value
16
XBRC MUX DP0 DP1 DP2 DP3
MUX DN0 DN1 DN2 DN3
16
XAA
16
X memory
DMX
16
16
16
Main bus (16 bits)
16 16 16 16 16
X data bus Y data bus
DMY
DN4 DN5 DN6 DN7
16 16 16
DP4 YAA DP5 DP6 DP7
16
Y memory
16
MUX YBRC
16
MUX
16
Immediate value
Immediate value
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3.5.2 Data memory space
The devices of the PD7701x family have two independent data memory spaces, X and Y, to which data can be accessed flexibly. Each of the X and Y data memory spaces is divided into internal memory and external memory areas. The internal memory area can always be accessed at high speeds as an internal resource of the device. The internal memory areas of both the X and Y memory spaces can be accessed simultaneously. The external memory area allows connection of memories of various speed range, using the incorporated software and hardware wait functions. In addition, the internal memory area is further divided into ROM and RAM areas. This subsection describes the memory spaces.
(1) X and Y memory spaces
The devices of the PD7701x family have two independent data memory spaces: X and Y. These spaces are respectively accessed via the X and Y data buses described earlier in this chapter (refer to section 3.2.2 "Data bus"). The features of these memory spaces are as follows: * One word consists of 16 bits. * Both X and Y spaces have 64K words. Although the memory maps of the X and Y memory spaces are the same, there are some differences among the products in the PD7701x family. The following figure shows the X and Y memory maps of each product in the family.
Figure 3-32. X/Y Data Memory Map
PD77016
0xFFFF
PD77015
External data memory (16K words)
PD77017
External data memory (16K words)
PD77018, 77018A, 77019Note
External data memory (16K words) System (20K words)
0x7000 0x6FFF
0xC000 0xBFFF
External data memory (48K words)
0x4800 0x47FF 0x4000 0x3FFF 0x3840 0x383F 0x3800 0x37FF
System (30K words)
0x5000 0x4FFF
System (28K words)
System (1984 words) Peripheral (64 words) System (12K words) Data RAM (2K words)
0x0400 0x03FF
Data ROM (2K words) System (1984 words) Peripheral (64 words) System (13K words) Data RAM (1K words)
Data ROM (4K words) System (1984 words) Peripheral (64 words) System (12K words)
Data ROM (12K words) System (1984 words) Peripheral (64 words) System (11K words) Data RAM (3K words)
0x0800 0x07FF 0x0000
0x0800 0x07FF
Data RAM (2K words)
0x0C00 0x0BFF
Caution No program or data must be stored to the addresses reserved for the system, nor must these addresses be accessed. If any of these addresses is accessed, normal operation of the PD7701x family is not guaranteed. Note The PD77019-013 does not have the internal ROM of the PD77019.
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(2) Internal data memory
As shown by the memory map in Figure 3-32, a 16K-word area starting from address 0 functions as an internal area of the PD77016. With the PD77015, 77017, 77018, 77018A, and 77019, a 48K-word area starting from address 0 is used as the internal area. The internal area is divided into a ROM area, RAM area, peripheral area, and system area, of which the ROM and RAM areas are used as a data memory. The capacity of the internal data memory differs by processor type, which allows users to select the device best suited to their application. For the details of the peripheral area, refer to section 3.7.2 "Peripheral registers".
Caution
Accessing system areas is prohibited.
(a) Internal ROM and RAM As described above, the capacities of the internal ROM and RAM areas can be selected. The table below lists the available capacity options. Note that the internal ROM of the PD77019-013 cannot be used.
Table 3-18. ROM and RAM Capacities
ROM Part number X None 2K words 4K words 12K words Y None 2K words 4K words 12K words RAM X 2K words 1K words 2K words 3K words Y 2K words 1K words 2K words 3K words
PD77016 PD77015 PD77017 PD77018 PD77018A PD77019
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(3) External data memory interface
(a) External data memory capacity As shown in Figure 3-32, the PD7701x family can expand the memory capacity by using an external data memory. The expandable capacity differs by processor type, as shown in the table below.
Table 3-19. Capacity of External Data Memory
Part number X external data memory 48K words 16K words Y external data memory 48K words 16K words
PD77016 PD77015 PD77017 PD77018 PD77018A PD77019
(b) Interface signals of external data memory When using the external data memory, bear in mind the following differences from the internal data memory: * As described in section 3.2.2 "Data bus", the external data bus is shared by the X and Y data buses. Therefore, the X and Y spaces, which are logically separated when viewed from the program, can be considered as a single memory space if the X/Y select signal is regarded as one of the address bits. * An wait function is available which is effected by the data memory wait cycle register (DWTR) and the WAIT pin. The external data memory interface uses the following pins: <1> DA0-DA15 (address output pins) These output pins constitute a 16-bit address bus. Note, however, that the PD77015, 77017, 77018, 77018A, and 77019 are not provided with the DA14 and DA15 pins. All these pins go into a high-impedance state while the bus is released. They output a low level immediately after reset. The statuses of these pins are not changed when the external data memory is not accessed (address output continues). <2> X/Y (X/Y output pin) This pin outputs a low level if the address bus DA0-DA15 accesses the X memory space; it outputs a high level if the Y memory is accessed. This pin goes into a high-impedance state while the bus is released.
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<3> D0-D15 (data input/output pin) These pins constitute a 16-bit data bus. They go into a high-impedance state while the bus is released, or when the external data memory is not accessed. <4> MRD (memory read output pin) This pin outputs the read strobe signal for the external data memory. It goes into a high-impedance state while the bus is released. Data is latched and MRD is switched in synchronization with the rising edge of CLKOUT. <5> MWR (memory write output pin) This pin outputs the write strobe signal for the external data memory. It goes into a high-impedance state while the bus is released. Data is output and MWR is switched in synchronization with the rising edge of CLKOUT. <6> WAIT (wait input pin) The PD7701x inserts wait cycle(s) if this pin is made low when the external data memory is accessed. <7> HOLDRQ (bus hold request input pin) This pin inputs a signal requesting occupancy of the bus. It is used to arbitrate the bus in a system where two or more CPUs, including the PD7701x, shares the bus. When this signal is made low, the bus is released to an external device after the current bus cycle has been completed. <8> BSTB (bus strobe output pin) This pin outputs a signal requesting use of the external data bus. When the bus is controlled by the PD7701x serving as a bus master, this signal functions as a bus strobe signal and indicates that the bus is accessed. In the bus slave status, this signal functions as an external data bus request signal in response to the HOLDRQ signal output by a bus master. <9> HOLDAK (bus hold acknowledge output pin) This pin outputs a signal permitting an external device to use the bus. It outputs a low level while the bus is released to an external device.
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Table 3-20. Pin Status
Pin I/O During reset L H Hi-Z H H - - H previous Initial after reset L L Hi-Z H H - - H previous No external memory access DA0-DA15 (13Note) O X/Y D0-D15 MRD MWR WAIT HOLDRQ BSTB HOLDAK O I/O O O I I O O previous previous Hi-Z H H - - H H During bus release Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - L H/L L
Note The PD77015, 77017, 77018, 77018A, and 77019 are not provided with DA14 and DA15.
(c) Data memory access timing Figure 3-33 (a) shows a read cycle without wait cycles, and Figure 3-34 (a) shows a write cycle without wait cycles. Figure 3-33 (b) shows a read cycle with wait cycles, and Figure 3-34 (b) shows a write cycle with wait cycles. If data memory read cycles are successively generated, MRD remains low.
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Figure 3-33. Timing of Data Memory Read Cycle (a) Without wait cycles
CLKOUT
tdDA
DA0-DA15, X/Y tsuDDRD thDDRD
D0-D15
tdDR
thDR
MRD
(b) With wait cycles
CLKOUT
tdDA
DA0-DA15, X/Y
tsuDDRD thDDRD
D0-D15
tdDR
thDR
MRD
tsuWA
thWA
tsuWA
thWA
WAIT
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Figure 3-34. Timing of Data Memory Write Cycle (a) Without wait cycles
CLKOUT tdDA DA0-DA15, X/Y tvDDWD tvDDWD thDDWD
D0-D15 tsuDW twDWH
tdDW twDWL MWR
(b) With wait cycles
CLKOUT tdDA DA0-DA15, X/Y tvDDWD D0-D15 tdDW twDWL MWR tsuWA WAIT thWA tsuWA thWA tsuDW twDWH tvDDWD thDDWD
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(d) Wait controller The wait controller enables access of an external data memory with a long access time, and inserts wait cycle(s) during external data memory access cycles. This wait function can be controlled in the following two ways: * By hardware signal pin The WAIT pin is provided, so that any number of wait cycles can be inserted by means of handshaking by hardware. * By DWTR (data memory wait cycle register) The number of wait cycles specified in advance by software can be set to DWTR which is mapped to the memory space as a peripheral register. The WAIT signal is a negative logic input signal and is sampled at the rising edge of CLKOUT when the external data memory is accessed. While this signal is active (low level), the corresponding cycle serves as a wait cycle (refer to (c) "Data memory access timing"). <1> DWTR (data memory wait cycle register) DWTR is a register that implements a programmable wait function controlled by software. This register is provided as one of the peripheral registers. The number of wait cycles specified in advance can be selected and set to this register by the application program. DWTR is a 16-bit register and is divided into fields as follows, for each processor type: * The DWTR of the PD77016 consists of six fields of two bits each. These six fields correspond to six 16K-word banks corresponding to the external memory. The six 16Kword banks are created by dividing each of the 64K-word external X and Y memory spaces by four. For each bank, the number of wait cycles can be set independently. * The DWTR of the PD77015, 77017, 77018, 77018A, and 77019 consists two 2-bit fields, which correspond to the two 16K-word banks external X and Y memory. The two 16K-word banks are created by dividing each of the 64K-word external X and Y memory space by four. For each bank, the number of wait cycles can be set independently. Figure 3-35 (a) shows the image of controlling the DWTR of the PD77016. Figure 3-35 (b) shows the image of controlling the DWTR of the PD77015, 77017, 77018, 77018A, and 77019. Table 3-21 shows the relations between the value set to each field of DWTR and the number of wait cycles.
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Figure 3-35. Data Memory Control Bank and DWTR Field Configuration (a) PD77016
X data memory 0xFFFF D field 16K words 0xC000 0xBFFF C field 16K words 0x8000 0x7FFF B field 16K words 0x4000 0x3FFF 0x0000 15 14 DWTR H field 13 12 11 10 9 8 7 0x4000 0x3FFF 0x0000 6 5 4 3 2 1 0 0x8000 0x7FFF F field 16K words 0xC000 0xBFFF G field 16K words 0xFFFF H field 16K words Y data memory
G field
F field
D field
C field
B field
(b) PD77015, 77017, 77018, 77018A, 77019
X data memory 0xFFFF D field 16K words 0xC000 0xBFFF 0x8000 0x7FFF 0x4000 0x3FFF 0x0000 15 14 DWTR H field 13 12 11 10 9 8 7 0xC000 0xBFFF 0x8000 0x7FFF 0x4000 0x3FFF 0x0000 6 5 4 3 2 1 0 0xFFFF H field 16K words Y data memory
D field
Caution
* With the PD77016, writing data to bits 9, 8, 1, and 0 is ignored. These bits are undefined when read. * With the PD77015, 77017, 77018, 77018A, and 77019, writing data to bits 13-8 and 5-0 is ignored. These bits are undefined when read.
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Table 3-21. Set Value of DWTR Field and Number of Wait Cycles
Bit 0 0 Wait cycles 0 Remark 1-cycle access: SRAM etc. with an access time of about 8 ns is connected (at 33 MHz). 0 1 1 2-cycle access: SRAM etc. with an access time of about 35 ns is connected (at 33 MHz). 1 0 3 4-cycle access: SRAM etc. with an access time of about 85 ns is connected (at 33 MHz). 1 1 7 8-cycle access: Mask ROM etc. with an access time of about 150 ns is connected (at 33 MHz)
Caution
When DWTR is set, the specified number of wait cycles becomes valid when an instruction immediately after the instruction that has set the data to DWTR is executed.
<2> Overlapping operation by WAIT pin and DWTR If the hardware control by the WAIT pin and the software control by DWTR are implemented simultaneously, the following operation is performed: (1) In the external data memory access cycle, the number of wait cycles specified by DWTR is unconditionally inserted. (2) At this time, the status of the WAIT pin is sampled at the rising edge of the last cycle of all the memory cycles. While the WAIT pin is active (low), wait cycles are continuously inserted.
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(e) Bus arbitration The PD7701x family is provided with the bus arbitration function to support memory configuration of multiple bus masters. It is considered that the typical multiple bus masters share the memory in the following combination: * PD7701x (master) * PD7701x - host CPU * PD7701x - DMA controller Care must be exercised if the supply voltage of each bus master differs from that of the others. Figure 3-36 shows a typical example of bus arbitration. The operations are as follows: <1> When the PD7701x family executes an instruction to access the common memory, BSTB becomes active (low). <2> The external device makes HOLDRQ active (low). <3> The PD7701x family makes HOLDAK active after the bus cycle has been completed (after the accesses are completed if accesses are successively generated). <4> The external device uses the bus. <5> The external device makes HOLDRQ inactive (high) after completing access. <6> The PD7701x family makes HOLDAK inactive (high) to resume bus access. - PD7701x (slave)
Figure 3-36. Bus Arbitration Procedure
CLKOUT (output) Bus idle
Note 1
Bus released
BSTB (output) HOLDRQ (input) HOLDAK (output)
X/Y (output) DA0-DA15 (output) D0-D15 (I/O)
<1>
<2>
<5>
<3> Hi-Z
<6>
Note 2
Note 3
External device access
<4> Note 1. BSTB becomes high when the last access has been completed. 2. External memory access: the last access if successible accesses are generated. 3. Previous value: i.e., not Hi-Z (no external memory access).
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(4) Restriction of simultaneous access
As described earlier, the PD7701x family divides its memory space in various ways. The PD7701x family has a function to access two memory spaces, X and Y, simultaneously by means of parallel load, etc. This paragraph describes the combination of memory spaces in which access can be made. Table 3-22 shows the combination of memory spaces which can be simultaneously accessed.
Table 3-22. Simultaneous Access to X and Y Memory Spaces
X memory area via X data bus Internal ROM Y memory area via Y data bus Internal ROM Internal RAM External memory Peripheral register -- OK -- OK Internal RAM OK OK OK OK External memory -- OK -- OK Peripheral register OK OK OK --
Remark OK : Can be simultaneously accessed -- : Cannot be simultaneously accessed
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3.5.3 Addressing mode
The PD7701x family is provided with a powerful architecture to realize high-speed, flexible data memory access. The X and Y memory areas are addressed by completely independent but functionally identically addressing units. This subsection describes the architecture and addressing modes implemented.
(1) Function of each part of addressing unit
The functions of the registers and functional blocks shown in Figure 3-31 are as follows: (a) Data pointers (DP0-DP7) These eight 16-bit registers are used for indirect addressing. DP0-DP3 are used to specify an address of the X memory space, while DP4-DP7 are used to specify an address of the Y memory space. The values of DP0-DP7 can be input/output via the main bus. (b) Index registers (DN0-DN7) These eight 16-bit registers modify DP0-DP7. After the memory has been accessed, DPn is modified by the value of DNn (n: 0-7, each corresponds respectively). The values of DN0-DN7 can be input/output via the main bus. The valid number range of this register is given by -32768 (0x8000) to +32767 (0x7FFF). (c) Modulo registers (DMX, DMY) These two 16-bit registers specify the ring count range when DP0-DP7 are modified during the ring count operation performed. The ring count range for DP0-DP3 is specified by DMX. DMY is used to specify that for DP4-DP7. The values of DMX and DMY can be input/output via the main bus. The valid number range of this register is given by +1 (0x0001) to +32767 (0x7FFF). (d) Address ALUs (XAA, YAA: X and Y Address ALUs) These two 16-bit ALUs are used to modify DP0-DP7. XAA is used to modify DP0-DP3, while YAA modifies DP4-DP7. (e) Bit reverse circuits (XBRC, YBRC: X and Y Bit Reverse Circuits) When a bit reverse access is performed, these circuits output an address that reverses the order of the DP0-DP7 values, so that the highest bit becomes the lowest, and vice versa. (f) Multiplexer (MUX) This circuit selects one of several signals for output.
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(2) Types of addressing modes
The data memory addressing modes are hierarchically classified below. There are one type of direct addressing mode and seven types of indirect addressing modes that are implemented by using data pointers (DPs) as the base address indicator. * Direct addressing * Indirect addressing * DPn (no change) * DPn++ (post increment) * DPn- - (post decrement) * DPn## (post index addition) * DPn%% (post modulo index addition) * !DPn## (pre-bit reverse and post index addition) * DPn##imm (immediate addition) (a) Direct addressing Direct addressing is to directly express an address value and address division (X or Y) in an instruction word. Data of 16 bits is exchanged between a specified address of a specified division (X or Y) and a general-purpose register via X or Y data bus. For details, refer to "PD7701x Family User's Manual Instructions". Example 1: Load
R0H = *0x1234:X; 16-bit data is loaded to the H part (middle 16 bits) of general-purpose register R0 from address 0x1234 of the X memory. Example 2: Store
*0x1234:X = R0H; 16-bit data is stored to address 0x1234 of the X memory from the H part (middle 16 bits) of general-purpose register R0.
Caution
The X and Y memory spaces cannot be accessed simultaneously by means of direct addressing.
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(b) Indirect addressing In all the indirect addressing modes, the DPn register (data pointer) is used. The basic features of indirect addressing are summarized below.
* As the address value, the current value of specified DPn is output in all the modes except the bit reverse index addition mode. In the bit reverse index addition mode, the current value of the specified DPn is reversed and output (refer to Figure 3-37). * If it is specified to modify DPn, DPn is modified after the data memory has been accessed. * The modified DPn value, i.e. the new address, is effective from the next instruction onwards. * DPn alone cannot be modified. * If an immediate value has been set to DPn, either by an inter-register transfer or an immediate value set instruction, the new address is effective from the next but one following instruction (refer to "PD7701x Family User's Manual Instructions"). * DP0-DP3 are used to access the X memory space, and DP4-DP7 are used to access the Y memory space.
Each indirect addressing mode is described next. <1> *DPn (no change) The memory is accessed with the value of DPn. The value of DPn is preserved after the access has been completed. Example:
R1L = *DP0; 16-bit data is loaded from the X memory address indicated by the value of DP0 to the L part (lower 16 bits) of R1. <2> *DPn++ (post increment) The memory is accessed with the value of DPn. The value of DPn is incremented (+1) after the access has been completed. Example:
R2H = *DP4++; 16-bit data is loaded from the Y memory address indicated by the value of DP4 to the H part (middle 16 bits) of R2, and then the value of DP4 is incremented.
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<3> *DPn- - (post decrement) The memory is accessed with the value of DPn. The value of DPn is decremented (-1) after the access has been completed. Example:
R3E = *DP1--; 8-bit data (the lower 8 bits of the 16 bits) is loaded from the X memory address indicated by the value of DP1 to the E part (higher 8 bits) of R3, and then the value of DP1 is decremented. <4> *DPn## (post index addition) The memory is accessed with the value of DPn. After the access has been completed, the value of DNn is added to DPn. Note that the n-th index register DNn corresponds only to the n-th data pointer DPn (e.g. DN1 to DP1). The valid number range of DNn is given by -32768 (0x8000) to +32767 (0x7FFF). Example:
R4L = *DP5##; 16-bit data is loaded from the Y memory address specified by the value of DP5 to the L part (lower 16 bits) of R4, and then the value of DN5 is added to DP5. <5> *DPn%% (post modulo index addition) The memory is accessed with the value of DPn. After the access has been completed, the value of DNn is added to DPn. In addition, modulo adjustment is made by DMX or DMY (DMX is used when n=0-3, and DMY is used when n=4-7). Note that the n-th index register DNn corresponds only to the n-th data pointer DPn (e.g. DN1 to DP1). The valid number range of DNn is given by -32768 (0x8000) to +32767 (0x7FFF). For the details of modulo index addition and modulo adjustment, refer to <9> "Modulo index addition and cyclic buffer". Example:
R5H = *DP3%%; 16-bit data is loaded from the X memory address specified by the value of DP3 to the H part (middle 16 bits) of R5. Then the value of DN3 is added to DP3, and modulo adjustment is made by DMX.
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<6> *!DPn## (pre-bit reverse and post index addition) The memory is accessed by using the value that reverses the order of the DPn values, as shown in Figure 3-37, and the value of DNn is added to DPn after the access has been completed. Note that the value of DNn having the same number as that of DPn must be added to DPn (for example, DN1 to DP1). This function is suitable for applications such as FFT.
Figure 3-37. Reversing Bits of DPn
DPn
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
* *
* *
* *
* *
* *
* *
* *
* *
Example:
R6H = *!DP6##; 16-bit data is loaded from the Y memory address specified by the reserved bits of DP6 to the H part (middle 16 bits) of R6, and then value of DN6 is added to DP6.
Remark DPn is not modified by bit-reversed access to the address, and the bit-reversed address is not fed back to DPn. After bit-reversed access, the value of DNn is added to the value of DP6 (original DP6 value) before bit reversion.
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<7> *DPn##imm (post immediate addition) The memory is accessed with the value of DPn, and immediate value imm is added to DPn after the access has been completed. The valid number range of imm is given by -32768 (0x8000) to +32767 (0x7FFF). Example:
R7L = *DP2##100; 16-bit data is loaded from the X memory address specified by the value of DP2 to the L part (lower 16 bits) of R7, and then immediate value "100" is added to DP2.
Caution
The immediate addition addressing mode cannot be used to access the X and Y memories simultaneously.
<8> Modifying data pointers Table 3-23 summarizes how the data pointers are modified as a result of accessing the memory in the above addressing modes.
Table 3-23. Modifying Data Pointers
(a) Operation
Example DPn DPn++ DPn- - DPn## Operation No modification DPn <-- DPn + 1 DPn <-- DPn - 1 DPn <-- DPn + DNn (Values of corresponding DN0-DN7 are added to DP0-DP7). Example: DP0 <-- DP0 + DN0 DPn%% (n=0-3) (n=4-7) !DPn## DPn = ((DPL + DNn) mod (DMX + 1)) + DPH DPn = ((DPL + DNn) mod (DMY + 1)) + DPH
Reverses bits of DPn and then accesses memory. After memory has been accessed, DPn <-- DPn + DNn
DPn##imm
DPn <-- DPn + imm
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(b) Value range
Hexadecimal DPn DNn DMX/DMY imm 0x0000 to 0xFFFF 0x8000 to 0x7FFF 0x0001 to 0x7FFF 0x8000 to 0x7FFF Decimal 0 to +65535 -32768 to +32767 1 to +32767 -32768 to +32767
<9> Modulo index addition and cyclic buffer The modulo index addition mode is provided for configuring a cyclic buffer (also called a ring buffer).
* Rule of operation After the memory has been accessed by using the value of DPn, DPn is modified. At this time, the operation is performed according to the following rules: (1) Executes operation of DPL = DPL + DNn. (2) If DPL DMa as a result, DPn = DPL + DPH is treated as the operation result. If not (i.e., when DPL > DMa), DPn = (DPL + DNn) mod (DMa + 1) + DPH is treated as the operation result. Where, DPH : lower k bits of the initial value of DPn, which is 0, if the value of DMa is in the range of [2k, 2(k-1)] (Refer to Figure 3-38.) DPL : value of lower k bits of DPn in the above case (Refer to Figure 3-38.) DMa : specified DPn corresponding to DMX or DMY
Remark The process (2) above is called modulo adjustment.
Figure 3-38. Division of DPn
Bit 15 0 Bit 14 Bit k 0 Bit k-1 1 Bit k-2 D Bit 0 D
DMa
*********
******
******
DPn
Bit 15
Bit 14
*********
Bit k
Bit k-1
Bit k-2
******
Bit 0
DPH
DPL
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* Meaning The ordinary modulo operation can be considered as the mapping shown in Figure 3-39.
Figure 3-39. Mapping of Ordinary Modulo Operation
2M 2M - 1 2M - 2
* * * * * * * * * *
M+2 M+1 M M-1 M-2
* * *
M M-1 M-2
* * * * * * *
2 1 0
*
Domain (x)
Mapping y = x mod M
2 1 0 Range (y)
*
In contrast, modulo adjustment can be considered as the mapping shown in Figure 3-40.
Figure 3-40. Mapping of Modulo Adjustment
2M 2M - 1 2M - 2
* * * *
* * * *
M+2 M+1 M M-1 M-2
* * * *
* * * *
* * *
M M-1 M-2 M-3
2 1 0 Domain (x) xM Mapping y=x y = x mod (M+1)
2 1 0 Range (y)
The difference between the two in terms of the range is that the usable buffer size in Figure 3-39 is M, while it is M+1 in Figure 3-40, where the value set to DMa is M, because the range in this case corresponding to the size of the buffer. Consequently, the maximum buffer size of 0x8000 can be used, as described below, despite the maximum set value of DMa is 0x7FFF.
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* Operation range of ring count The first address of the range in which a ring count operation is executed in connection with the modulo index addition is determined by the values of the data pointer and modulo register. Where the value of the modulo register (DMX/Y) is 2k-1DMX/Y<2k, the starting address of the ring count operation is the 16-bit value whose higher "16-k" bits are the same as those of the data pointer and whose lower k bits are zeros. The end address is the value whose higher "16-k" bits are the same as those of the data pointer and whose lower k bits are the same as those of the modulo register. The higher "16-k" bits of the data pointer always remain unchanged.
Ring Count Operation Range
When DMa is set as follows,
15 DMa 0 0 ********* k 0 k-1 1 D ****** 0 D
"0"
ring count start address and end address are like follows.
15 Start address of DPn X X ********* k X k-1 0 ******** 0 0
DPH 15 End address of DPn X X ********* k X k-1 1 D
"0" 0 ****** D
DPH
Lower part (under k-1) of DMa
* Restriction Observe the following restrictions in executing modulo addressing: * Keep the range of DMa to [1-0x7FFF]. * Make sure that the absolute value of the value of DNn does not exceed DMa.
Caution
Because 0 cannot be set to DMa, a cyclic buffer with buffer size = 1 cannot be configured.
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* Example of modulo index addition An example of operation process when a cyclic buffer is configured by using modulo index addition is shown below.
Example 1. DMX=0x7; DN0=1; DP0=0x0; At this time, the value of DP0 is updated as follows by means of modulo index addition: DP0=0x0 0x0+1 DP0=0x1 0x1+1 DP0=0x2 0x2+1 DP0=0x3 0x3+1 DP0=0x4 0x4+1 DP0=0x5 0x5+1 DP0=0x6 0x6+1 DP0=0x7 0x7+1=0x8 0x8-(0x7+1)=0x0 DP0=0x0 0x0+1 DP0=0x1 0x1+1 DP0=0x2 0x2+1 DP0=0x3 0x3+1 DP0=0x4 :
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Example 2. DMX=0xA; DN0=3; DP0=0x10; At this time, the value of DP0 is updated as follows by means of modulo index addition: DP0=0x10 0x10+3 DP0=0x13 0x13+3 DP0=0x16 0x16+3 DP0=0x19 0x19+3=0x1C 0x1C-(0xA+1)=0x11 DP0=0x11 0x11+3 DP0=0x14 0x14+3 DP0=0x17 0x17+3 DP0=0x1A 0x1A+3=0x1D 0x1D-(0xA+1)=0x12 DP0=0x12 * * *
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3.6 Operation Unit
The general-purpose registers in this unit are source of all operands and destination of all results of arithmetic/logic operations. The general-purpose registers are connected to the * main bus for inter-register transfers * X and Y data bus for data exchange with the data memories and peripheral registers All kinds of arithmetic/logic operations which are part of the following instruction types are carried out in the operation unit: * trinomial instructions all operations which involve 3 input operands, e.g.
MADD:
R0 = R0 + R1H * R2H
* binomial instructions all operations which involve 2 input operands, e.g.
ADD:
R0 = R2 + R3
* monomial instructions all operations which involve 1 input operand, e.g.
NEG:
R0 = -R1
The section describes in details the functions and data formats of the general-purpose registers R0-R7, of the multiplier /accumulator MAC and the MAC input shifter MSFT, of the arithmetic/ logic unit ALU, and of the barrel shifter BSFT. For the block diagram of this unit, refer to section 3.6.1 "Block configuration".
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3.6.1 Block configuration
Figure 3-41 is the block diagram of the operation unit.
Figure 3-41. Operation Unit
X data bus (16 bits)
Y data bus (16 bits)
16 16
Immediate value
40 40 40 16
MUX 0/1/16 bits R0-R7 (40 bits x 8) MAC
40
40
MSFT
16
16 40
ALU
BSFT
16
Main bus (16 bits) R0-R7: MAC: MSFT: ALU: BSFT: General-purpose registers Multiply accumulator MAC input shifter Arithmetic logical unit Barrel shifter
3.6.2 General-purpose registers and data formats
The features of the general-purpose registers are as follows: * 40-bit registers * Eight registers (R0-R7) available * Function as input/output parameters of operation instructions (only general-purpose registers, in addition to immediate data, can be described as parameters of operation instructions) * Exchange data with X and Y data memories and peripheral registers (load/store function) * Transfer data with other registers
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(1) Partitioning of the general-purpose registers
Although a general-purpose register consists of 40 bits, the register is divided into three parts, as follows, so that only a specified part of the register can be used to transfer and load/store data or to execute arithmetic operations. In this case, the three parts are exclusive to each other. * L part : bits 15-0 (lower 16 bits) * H part : bits 31-16 (middle 16 bits) * E part : bits 39-32 (higher 8 bits) Depending on the type of arithmetic/logic operation respectively data transfer different parts of a general-purpose register are involved, as shown in Table 3-24. The figure below shows these five formats (except R0HL-R7HL) with assembly names.
Table 3-24. Formats of General-purpose Registers
R0-R7 40 bits MAC multiply/accumulate X MAC exclusive multiply ALU BSFT X/Y bus transfer inter-register transfer X X X X - R0L-R7L R0H-R7H R0E-R7E 16 bits 16 bits 8 bits X - - X X X X X - - X - - - - - X - R0HL-R7HL 32 bits - - X - - - R0EH-R7EH 24 bits - - - - X -
Figure 3-42. Formats of General-purpose Registers
39 R0-R7 39 R0EH-R7EH 39 R0E-R7E 39 R0H-R7H 39 R0L-R7L X X D 32 31 D 16 15 D 32 31 X 16 15 X 0 0 D D 16 15 X 0 0 0
Remarks D: numeric value X: invalid
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Figure 3-43 shows data exchange between general-purpose registers and data memory.
Figure 3-43. Data Exchange between General-purpose Registers and Data Memory
Number format in general register Operation examples General-purpose register Memory 15 16 bit unsigned Unsigned multiply increment, decrement x/y memory rl 39 re 15 16 bit signed fixed point without sign extension Signed multiply rh 39 S. 3231 S. 15 Extension Store/restore of 40 bit numbers 0 1615 0 rh 3231 rh 0 1615 rl 0 rl Memory General-purpose register 0
re
39
3231
1615
0
re
15 S 16 bit signed fixed point with sign extension Signed multiply - 39 S 15 S 40 bit signed fixed point MAC/ALU operations barrel shifter - 39 S 3231 3231
0
1615
0
reh
0
1615 0
0
ro
Remarks
Changed Unchanged
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(2) Numeric format
The general-purpose registers of the PD7701x family can process fixed-point and integer data. The architecture places an emphasis on operations of fixed-point data, however. (a) Fixed-point format The fixed-point format uses the position between bits 31 and 30 as the decimal point. Fixed-point data can be expressed in three ways: in 40-bit, 32-bit, and 16-bit units.
40-bit data format (input for addition/subtraction/and/or/xor)
39 38 S 31 30 0 D
.
0x80'0000'0000 to 0x7F'FFFF'FFFF (-256 to (+256-2 -31 ))
S: sign D: numeric value X: invalid
32-bit data format (input for exponent instruction)
39 X 32 31 S 0 D
.
0x800'0000 to 0x7FFF'FFFF (-1 to (+1-2-31 ))
16-bit data format (input for multiplication instruction)
39 X 32 31 S 16 15 D 0x8000 to 0x7FFF (-1 to (+1-2-15 ))
Remark The absolute value of data never exceeds 1 in the 32-bit fixed-point format or 16-bit fixed-point format. As long as an accumulative operation is executed on a general-purpose register with these formats as operands, therefore, the E part functions as an overflow absorbing area (called a head room). This function allows omission of judgment of overflow when 256 accumulative operations are performed even if it is assumed that an overflow of 1LSB (of the E part) occurs as a result of one accumulative operation.
0 X
.
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(b) Integer format The integer format is illustrated below.
16-bit data format (input for multiplication and shift instructions)
39 X 16 15 D 0x0000 to 0xFFFF (0 to 65535) 0
D: numeric value X: invalid
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3.6.3 Operation functions of multiply accumulator (MAC) and MAC input shifter (MSFT)
The multiply accumulator performs the following functions: * Multiplication MPY: ro = rh * rh'
* Extends multiplication and its result to 40 bits and adds the result to specified generalpurpose register MADD: MSUB: SUMA: UUMA: ro ro ro ro = = = = ro ro ro ro + - + + rh rh rh rl * * * * rh' rh' rl rl' (signed-signed multiply) (signed-signed multiply) (signed-unsigned multiply) (unsigned-unsigned multiply)
* Extends multiplication and its result to 40 bits and adds the result to the result of shifting specified general-purpose register 1/16 bits to the right
MAS1:
ro = (ro>>1)
+ rh * rh'
MAS16: ro = (ro>>16) + rh * rh'
Caution
MAC, ALU, and BSFT cannot operate simultaneously.
(1) Multiplication function
The multiplication function is implemented by the multiply accumulator (MAC). This function can be implemented in the following three ways, depending on the data type to be handled: * Signed-signed multiply * Signed-unsigned multiply * Unsigned-unsigned multiply
(a) Signed-signed multiply Both of the two operands are of signed 16-bit fixed-point type. Therefore, data is set to the H part of a general-purpose register whose bit 31 indicates the sign. A representation of this operation process is illustrated in Figure 3-44.
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Figure 3-44. Signed-Signed Multiply
MPY: ro = rh * rh' 39 rh 32 31 30 S. 0xxx'8000'xxxx to 0xxx '7FFF'xxxx (-1 to (+1-2-15 )) x 32 31 30 16 15 S. 0xxx'8000'xxxx to 0xxx '7FFF'xxxx (-1 to (+1-2-15 )) = 32 31 30 16 15 16 15 0
39 rh'
0
39 ro S
0
.
0xFF'8001'0000 to 0x00'8000'0000 ((-1-2-15 ) to +1)
Remarks 1. If multiplication between 0x8000 (-1) is executed, the result is 0x00'8000'0000. However, because +1 cannot be expressed in the range of the 32-bit fixed-point format, an overflow occurs (extension bit re = 0x00 is different from the sign bit of the 32-bit format in this case). However, the value is accurate when viewed from the point of the 40-bit format (0x00'8000'0000 = +1). 2. Since a multiplication of two 16-bit values produces maximum 31 valid bits, the LSB of the result registers is always 0.
(b) Signed-unsigned multiply One of the two operands is set to the H part of a general-purpose register in the 16-bit fixed-point type, where bit 31 of the register indicates a sign. The other parameter is set to the L part of a general-purpose register in the integer format. Figure 3-45 shows the image of this operation process.
Figure 3-45. Signed-Unsigned Multiply
Part of SUMA: ro = rh * rl 39 rh 32 31 30 S. 0xxx'8000'xxxx to 0xxx'7FFF'xxxx (-1 to (+1-2 -15 )) x 32 31 16 15 16 15 0
39 rl
0
.
0xxx'xxxx'0000 to 0xxx'xxxx'FFFF (0 to (+2-2 -15 )) = 39 32 31 30 16 15 0
ro
S
.
0xFF'0001'0000 to 0x00'FFFD'0002 (- (2-2 -15 ) to (+1-2 -15) (+2-2 -15))
Caution
There is no exclusive instruction that executes this operation. This operation is performed as part of the signunsign multiply add instruction.
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(c) Unsigned-unsigned multiply Both of the two operands are set to the L parts of general-purpose registers in the integer format. Figure 3-46 shows the image of this operation process.
Figure 3-46. Unsigned-Unsigned Multiply
Part of UUMA: ro = rl * rl' 39 rl 0xxx'xxxx'0000 to 0xxx'xxxx'FFFF (0 to (+2-2 x 32 31 16 15
-15
32 31
16 15
0
.
)) 0 39
rl' 0xxx'xxxx'0000 to 0xxx'xxxx'FFFF (0 to (+2-2 = 39 ro 0x00'0000'0000 to 0x01'FFFC'0002 (0 to (+2-2
-15 2 -15
.
)) 10
32 31
16 15
.
))
Caution
There is no exclusive instruction that executes this operation. This operation is performed as part of the unsign-unsign multiply add instruction.
(2) Accumulative multiplication function (trinomial operation)
All the trinomial operations executed by the PD7701x family are accumulative multiplication. The accumulative multiplication can be implemented in the following three ways, depending on the shift command to the register that is used for the accumulative operation (two accumulative operations, accumulative addition and accumulative subtraction, can be executed, however). At this time, the shift processing is executed by the MAC input shifter (MSFT). * Accumulative multiplication * 1-bit shift accumulative multiplication * 16-bit shift accumulative multiplication The accumulative multiplication can also be classified into the following three types by the data type of the parameters used for the operation: * Signed-signed multiply * Signed-unsigned multiply * Unsigned-unsigned multiply
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In all, therefore, the following six types of trinomial operation instructions are available: * Multiply add (signed-signed multiply and accumulative add) * Multiply sub (signed-signed multiply and accumulative sub) * Sign-unsign multiply add (signed-unsigned multipy and accumulative add) * Unsign-unsign multiply add (unsigned-unsigned multiply and accumulative add) * 1-bit shift multiply add (signed-signed multiply and accumulative add after 1-bit shift) * 16-bit shift multiply add (signed-signed multiply and accumulative add after 16-bit shift) The accumulative multiplication function implements trinomial operations where three parameters are used. Of these, two are the parameters for multiplication and the other is for accumulative operation. General-purpose registers are specified for these parameters. In this case, registers can be specified in duplicate. Table 3-25 shows these combination.
Table 3-25. Accumulative Multiplication Function
Signed-signed MSFT 0 bit Multiply/ accumulate MSFT 1 bit MSFT 16 bit Exclusive multiply (Binomial operation) ro = ro rh * rh' (MADD, MSUB) ro = (ro>>1) + rh * rh' (MAS1) ro = (ro>>16) + rh * rh' (MAS16) ro = rh * rh' (MPY) Signed-unsigned ro = ro + rh * rl (SUMA) -- -- -- Unsigned-unsigned ro = ro + rl * rl' (UUMA) -- -- --
(a) Accumulative multiplication The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to respectively subtracted from a 40-bit fixed-point operand. The related instructions are:
MADD: MSUB:
ro = ro + rh * rh' ro = ro - rh * rh'
Figure 3-47 shows the image of this operation.
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Figure 3-47. Accumulative Multiplication
39 ro S 32 31 30 16 15 0
.
32 31 30 S. x 16 15 0
39 rh
39 rh'
32 31 30 S. =
16 15
0
39 ro S
32 31 30
16 15
0
.
(b) 1-bit shift accumulative multiplication The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a 1 bit right shifted 40-bit fixed-point operand. The related instruction is:
MAS1:
ro = (ro>>1) + rh * rh'
Figure 3-48 shows the image of this operation:
Figure 3-48. 1-Bit Shift Accumulative Multiplication
39 ro S 32 31 16 15 0
.
1-bit arithmetic right shift
39 SS
32 31 30
16 15
0
.
+ 32 31 30 S 16 15 0
39 rh
.
x 16 15 0
39 rh'
32 31 30 S
.
= 16 15 0
39 ro S
32 31 30
.
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(c) 16-bit shift accumulative multiplication The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a 16 bit right shifted 40-bit fixed-point operand. The related instruction is:
MAS16:
ro = (ro>>16) + rh * rh'
Figure 3-49 shows the image of this operation:
Figure 3-49. 16-Bit Shift Accumulative Multiplication
39 ro S 16-bit arithmetic right shift 39 32 31 30 16 15 0 32 31 16 15 0
SSSSSSSS S . SSSSSSSS + 39 rh 32 31 30 S. x 39 rh' 32 31 30 S. = 39 ro S 32 31 30 16 15 0 16 15 0 16 15 0
.
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3.6.4 Operation functions of arithmetic and logic unit (ALU)
The arithmetic and logic unit (ALU) executes an arithmetic or logical operation on two or one 40-bit input data, and outputs one 40-bit data. As both two operands for a binomial operation, general-purpose registers can be specified, or a register can be specified as one of the operands with immediate data specified as the other (immediate data cannot be used with the LT instruction, however). If general-purpose registers are specified as both operands, they can be in duplicate. Any general-purpose register can be specified for a monomial operation. It is also possible to specify any generalpurpose register to store the result of the operation.
Caution
MAC, ALU, and BSFT cannot operate simultaneously.
(1) Arithmetic operation instruction
(a) Binomial arithmetic operation The following binomial arithmetic operation instructions are available. For each instruction, refer to "PD7701x Family User's Manual Instructions." * Multiply instruction (MPY: executed by MAC) * Add instruction (ADD) * Immediate add instruction (IADD) * Subtract instruction (SUB) * Immediate subtract instruction (ISUB) * Less-than instruction (LT) (b) Monomial arithmetic operation The following monomial arithmetic operation instructions are available. For each instruction, refer to "PD7701x Family User's Manual Instructions." * Clear instruction (CLR) * Increment instruction (INC) * Decrement instruction (DEC) * Absolute value instruction (ABS) * Two's complement instruction (NEG) * Clip instruction (CLIP) * Round instruction (RND) * Exponent instruction (EXP) * Substitute instruction (PUT) (mainly used for data transfer between general-purpose registers) * Accumulative addition instruction (ACA) * Accumulative subtraction instruction (ACS) * Division instruction (DIV)
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(2) Logical operation instruction
(a) Binomial logical operation The following binomial logical operation instructions are available. For each instruction, refer to "PD7701x Family User's Manual Instructions." * And instruction (AND) * Immediate and instruction (IAND) * Or instruction (OR) * Immediate or instruction (IOR) * Exclusive or instruction (XOR) * Immediate exclusive or instruction (IXOR)
(b) Monomial logical operation The following monomial logical operation instruction is available. For each instruction, refer to "PD7701x Family User's Manual Instructions." * One's complement instruction (NOT)
Caution
The number range of immediate data is 0-0xFFFF (0-65536), and set to bit 15-0. Each operation is executed with 40-bit data that 39-16 are 0 extended to this immediate 16-bit data.
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3.6.5 Operation functions of barrel shifter (BSFT)
The barrel shifter (BSFT) executes shift operations. All the shift operations are binomial operations. The BSFT outputs any shift pattern as 40-bit data in one instruction cycle in response to 40-bit input data. As both two operands for a binomial operation, general-purpose registers can be specified, or a register can be specified as one of the operands with immediate data specified as the other. If general-purpose registers are specified as both operands, they can be in duplicate. Any general-purpose register can be specified for a monomial operation. It is also possible to specify any general-purpose register to store the result of the operation.
Caution
MAC, ALU, and BSFT cannot operate simultaneously.
(1) Shift operation instruction
All the shift operations are binomial operations. The following shift operations instructions are available. For each instruction, refer to "PD7701x Family User's Manual Instructions." * Arithmetic right shift instruction (SRA) * Immediate arithmetic right shift instruction (ISRA) * Logical right shift instruction (SRL) * Immediate logical right shift instruction (ISRL) * Logical left instruction (SLL) * Immediate logical left shift instruction (ISLL)
Caution
The number range of general-purpose register or immediate data as shift value is 0-0x27 (0-39), and set to bit 5-0. The values of bit 15-6 are ignored.
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(2) Shift operation function
Figure 3-50 shows each BSFT operations.
Figure 3-50. Barrel Shifter Operations
Shift number: n = 0 to 39, specified by - immediate value - bit 5-0 of rl part of general-purpose register * Arithmetic right shift: ro = ro' sra n, ro = ro' sra rl 39 ro' S re 3231 rh 1615 rl 0
39
3231
1615
0
n 39
arithmetic right shift 3231 1615 0
ro S S ... n x "S" * Logical right shift: ro = ro' srl n, ro = ro' srl rl 39 ro' re 3231 rh 1615 rl 0 39 "0" n 39 ro 00 ... n x "0" * Logical left shift: ro = ro' sll n, ro = ro' sll rl 39 ro' re 3231 rh 1615 rl 0 39 3231 1615 0 "0" n 39 ro 3231 logical left shift 1615 0 ...00 n x "0" 3231 logical right shift 1615 0 3231 1615 0
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3.7 Peripheral Units
3.7
Peripheral Units
The PD7701x family is provided with the five peripheral interface functions as listed below. * Serial interface * Host interface * General-purpose I/O port * Wait control functionNote 1 * Debug interfaceNote 2
Notes 1. Although the wait control function is not a peripheral function in terms of the general meaning of "peripheral", it is treated in the same manner as a peripheral control function with the PD7701x family. 2. The debug interface cannot be used by the user program.
When handling these peripherals from the user application, access the peripheral registers mapped to the internal memory area.
3.7.1 Block configuration
Figure 3-51 shows the block configuration of the peripheral units.
Figure 3-51. Peripheral Units
X data bus (16 bits)
SI1, SO1
Serial interface #1 Y data bus (16 bits)
SI2, SO2
Serial interface #2
HD0-HD7
Host interface
Wait controller
TDO TICE TCK TDI TMS
interface for debugging
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P0-P3
Port
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3.7.2 Peripheral registers
The internal peripheral units can be used by accessing the corresponding peripheral registers mapped in the internal data memory space. Table 3-26 shows the mapping of the peripheral registers in the memory space, and the outline of each register.
Table 3-26. Memory Mapping of Peripheral Registers
X/Y memory address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 0x3809 0x380A-0x383F Register name SDT1 SST1 SDT2 SST2 PDT PCD HDT HST DWTR IWTR Reserved Function Serial data register 1 Serial status register 1 Serial data register 2 Serial status register 2 Port data register Port command register Host data register Host status register Data memory wait cycle register Instruction memory wait cycle register Peripheral name SIO SIO SIO SIO IOP IOP HIO HIO WTR WTR -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W --
Do not access this area.
Cautions 1. The register names in this table are not reserved words of the assembler or C language. When using these names with the assembler or C language, the user must explicitly define them. 2. The same register can be accessed, as long as the address is the same, from both the X and Y memory spaces. 3. Even different registers cannot be accessed from both the X and Y memory spaces at the same time.
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3.7.3 Serial interface
The PD7701x family is provided with two channels of serial interfaces, both of which are of the same structure. The main features of these serial interfaces are as follows: * Clock supply Separate external clock for serial channels 1 and 2, common clock for serial input and output of one channel * Data word format Serial input/output data word length 8 or 16 bits, to specify separately for input and output of each channel MSB-first or LSB-first data format, to specify separately for input and output of each channel * Internal data bus connection Access of all registers via peripheral bus, connected to X and Y buses * Internal handshake Internal synchronization by means of polling, wait, or interrupt * External handshake External synchronization by means of dedicated status signals
Each serial interface control circuit (SCTL) controls the pins and registers for the serial interface. Figure 3-52 shows the block diagram of the serial interface.
Figure 3-52. Serial Interface
Peripheral bus (16 bits) 16 SDT1 (in) 16 16 SIS1 SOS1 SIS2 SOS2 16 SDT1 (out) 16 SST1 16 SDT2 (in) 16 16 16 SDT2 (out) 16 SST2
SCTL
SCTL
SI1 SO1
SCK1 SIEN1 SIAK1 SOEN1 SORQ1
SI2 SO2
SCK2 SIEN2 SIAK2 Note SOEN2 SORQ2 Note
Note Not provided to the PD77015, 77017, 77018, 77018A, and 77019.
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[Operational outline of serial interface] This section explains the internal logical operations of the serial interface of the PD7701x family (for detailed timing, refer to Figures 3-54 and 3-55). To transfer data through serial interface, double buffers are provided for both input and output. Serial input is performed by the following registers: * SIS register (serial input shift register) : Inputs serial data from the SI pin 1 bit at a time, and outputs 16-bit parallel data to SDT (in).
* SDT (in) register (serial data input register) : Inputs 16-bit parallel data from the SIS register and outputs 16-bit parallel data to the peripheral bus. Serial output is performed by the following registers: * SDT (out) (serial data output register) * SOS (serial output shift register) : Writes 16-bit parallel data from the peripheral bus and outputs 16-bit parallel data to SOS. : Inputs 16-bit parallel data from SDT (out) and outputs serial data from the SO pin 1 bit at a time.
The serial interface is accessed from an external device by using the 1-bit serial data input pin (SI) and output pin (SO). In the PD7701x, serial input/output is performed by using 8-/16-bit parallel input data register SDT (in) and output data register SDT (out). Because data transfer is automatically performed from SIS to SDT (in) and from SDT (out) to SOS, it does not have to be directly controlled by program. Internal flags are provided to synchronize serial data transfer and to monitor the status of each of the dedicated external pins and registers. * SIAK (serial input acknowledge) : This is an external pin that monitors the status of SIS. Input of new serial data can be started. Valid data still exists in SIS. New serial data cannot be input.
SIAK = high level (SIS is empty.) SIAK = low level (SIS is not empty.) * SORQ (serial output request)
: This is an external pin that monitors the status of SOS.
SORQ = high level (SOS is not empty.) Data to be output still exists in SOS. (Data can be output by making SOEN high.) SORQ = low level (SOS is empty.) No data to be output exists in SOS. * SLEF flag (serial load enable flag) : This flag monitors the status of SDT (in) (this is a flag in the serial status register (SST)). SLEF = 1 (SDT (in) is not empty.) SLEF = 0 (SDT (in) is empty.) Valid input data exists in SDT (in). Input data that can be loaded from SDT (in) does not exist.
* SSEF flag (serial store enable flag): This flag monitors the status of SDT (out) (this is a flag in the serial status register (SST)).
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SSEF = 1 (SDT (out) is empty.)
New output data can be stored to SDT (out).
SSEF = 0 (SDT (out) is not empty.) Valid output data still exists in SDT (out). Whether data can be actually transferred to the serial input pin (SI) and serial output pin (SO) after appropriate control signals and serial clock have been input is automatically determind by the internal hardware. * If an attempt is made to output serial data from the SO pin when the SOS register has no data (SORQ = low level), the SO pin goes into a high-impedance state. * If an attempt is made to input new serial data to the SIS register before the current data of the SIS register is transferred to the SDT (in) register (SIAK = low level), the new data is not written over the current data of the SIS register. In addition to this hardware control, loading from the SDT (in) register and storing to the SDT (out) register are completely controlled in software. Correctly load or store data by <1> checking SLEF/SSEF or <2> using an interrupt, so that valid data is not written over or that the same data is not loaded or stored two times. When successively inputting or outputting serial data, keep in mind the following points: (1) When polling with status flag Make sure that data transfer is not disrupted by always monitoring the status of the SLEF flag (status flag of SDT (in) register) or SSEF flag (status flag of SDT (out) register). (2) When using serial input interrupt If an interrupt occurs, immediately load serial data. (3) When using serial output interrupt Because the interrupt cannot be used when the first data is transferred (the same applies when a single data is output), do not use an interrupt for transfer. When inputting or outputting the next data and if an interrupt occurs, immediately store the serial data. Before storing the last data, disable the interrupt so that the next interrupt does not occur. The status of the serial input/output interface and operation block diagram are shown below.
Table 3-27. Status Indicators of Serial Input/output Interfaces
Register Status indicator SIS Serial output SDT(in) SLEF flag SIAK pin Status High: empty Low: not empty 1: 0: SOS Serial output SDT(out) SSEF flag SORQ pin not empty empty Comments Serial input accepted Serial input not accepted Data can be loaded from SDT(in) Data cannot be loaded from SDT(in) Serial output possible Serial output not possible Data can be stored to SDT(out) Data cannot be stored to SDT(out)
High: not empty Low: empty 1: 0: empty not empty
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Figure 3-53. Function Diagram of Serial Interface (1 channel)
Peripheral bus (16 bits) Load 16 INT 16 bit 1 bit 0 ************************ SST Reg.
SSEF SLEF
Store 16 INT
SDT (in) 16 SI SIAK SIEN SCK SIS Serial Parallel Parallel
SDT (out) 16 SOS Serial SO SORQ SOEN
(1) Pins of serial interface
The PD7701x has two sarial interface channels. The number suffixed to a serial interface pin indicates a channel. All the serial interface signals, except the clock and data signals, are active-high.
Remark The PD77015, 77017, 77018, 77018A, and 77019 are not provided with the SORQ2 and SIAK2 pins.
(a) SCK1 and SCK2 (serial clock - input) These are clock input pins for serial data input or output. Serial data are input and output, and serial interface signals are output and sampled in synchronization with the SCK signal. (b) SORQ1 and SORQ2 (serial output request - output) These pins output serial data output request signals. The output signals change its status at the rising edge of SCK. When serial data is written to the serial data output register, these pins are asserted active (high level). When SOEN and SORQ are asserted active, serial output is started. These pins are deasserted inactive (low level) after serial output has been started. These pins are deasserted inactive at hardware reset.
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(c) SOEN1 and SOEN2 (serial output enable - input) These pins input serial data output enable signals. These signals are sampled at the falling edge of SCK. They are asserted active (high level) when the external device is ready to input serial output data. When SOEN and SORQ are asserted active, serial output is started. (d) SO1 and SO2 (serial data output - output) These pins output serial data. The status of the output data changes at the rising edge of SCK. When output is completed, these pins go into a high-impedance state. (e) SIEN1 and SIEN2 (serial input enable - input) These pins input serial data input enable signals. These signals are sampled at the falling edge of SCK. They are asserted active (high level) when the external device is ready for outputting serial input data. Serial input is started when SIEN and SIAK are asserted active. (f) SIAK1 and SIAK2 (serial input acknowledge - output) These pins output serial data input acknowledge signals. These signals change its status at the rising edge of SCK. They are asserted active (high level) when serial input is ready. When SIEN and SIAK are asserted active, serial input is started. These signals are deasserted inactive (low level) after serial input has been started. These pins are deasserted inactive at hardware reset. (g) SI1 and SI2 (serial data input - input) These pins input serial data. The input data is sampled at the falling edge of SCK.
Table 3-38. Pins Status during and after Hardware Reset
Pin SCK1, 2 SORQ1, 2 SOEN1, 2 SO1, 2 SIEN1, 2 SIAK1, 2 SI1, 2 I/O I O I O I O O During reset -- L -- Hi-Z -- L -- After reset -- L -- Hi-Z -- L --
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(2) Registers of serial interface
The PD7701x has two serial interface channels. The number suffixed to the registers of the serial interface indicates the channel number. (a) SDT1 and SDT2 (serial data registers: 0x3800:X/:Y, 0x3802:X/:Y) A serial data register (SDT) is a 16-bit register that inputs or outputs serial data. A value can be input to or output from SDT by using a register-to-register transfer instruction. When 8-bit data is input or output, the serial data is input to or output from the higher 8 bits of SDT. <1> Serial data output register This is a 16-bit register that sets serial data to be output. When a store instruction is executed to SDT, data is input to this register from the peripheral bus. Output of SO can be selected from the MSB first or LSB first. When the serial output shift register (SOS) becomes empty. the value of this register is written to SOS. <2> Serial data input register This is a 16-bit register that reads serial input data. When an instruction to load data from SDT is executed, the data of this register is output to the peripheral bus. Whether the data is output with the MSB first or LSB first can be selected when the data is input. When the last bit is input to the serial input shift register (SIS), the value of SIS is written to this register. (b) SST1 and SST2 (serial status register: 0x3801:X/:Y, 0x3803:X/:Y) The serial status register (SST) is a 16-bit register that indicates the mode setting of serial input/output and status. This register indicates whether data is transferred with the MSB or LSB first, a bit length (16 or 8 bits), specification of interface with the PD7701x, overrun, and underrun. A value can be input to or output from SST by using a register-to-register transfer instruction. The value of this register is 0x0002 at reset. Table 3-30 shows the function of each bit of SST.
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Table 3-29. Conditions of Serial Input/output Error Flags Settings
Error flag SSER SLER Set condition Store to SDT while SSEF = 0 Load from SDT while SLEF = 0 Reset condition By hardware reset or by program
Changing serial output mode: The serial output mode (such as data length: 8 or 16 bits and LSB/MSB first) is determined by the setting of SST when data is stored to SDT (out). Do not change the value of SST when SSEF = 0 (when data exists in SDT (out)). Change the value of SST when SSEF = 1 (when SDT (out) is empty).
Changing serial input mode: Do not change the value of SST when serial input is under execution. If the serial successive input mode is set (SICM = ), clear SICM to 0 when SLEF = 1, change the serial input mode (such as data length: 8 or 16 bits and LSB/MSB first), and then set SICM to 1 again. The new value of SST becomes valid when data is input after the two data input to SDT (in) and SIS have been loaded.
(c) SOS1 and SOS2 (serial output shift registers) A serial output shift register (SOS) is a 16-bit shift register that outputs and shifts serial data from SO at the rising edge of serial clock SCK. When the specified number of bits have been output, new data is input from the serial data output register SDT (out). (d) SIS1 and SIS2 (serial input shift registers) The serial input shift register (SIS) is a 16-bit shift register that receives and shifts the data input from SI at the falling edge of serial clock SCK. When the specified number of bits have been input, data is output to serial data input register SDT (in).
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Table 3-30. Functions of SST (SST1:0x3801:X/:Y, SST2:0x3803:X/:Y)
Bit 15 Name SOTF Load/store (L/S) L/S Bit function Serial output transfer format setting bit * 0: Serial output with MSB first * 1: Serial output with LSB first Serial input transfer format setting bit * 0: Serial input with MSB first * 1: Serial input with LSB first Serial output word length setting bit * 0: 16-bit serial output * 1: 8-bit serial output Serial input word length setting bit * 0: 16-bit serial input * 1: 8-bit serial input SDT store wait enable bit * 0: Does not use store wait function. * 1: Uses store wait function. Inserts wait cycles when PD7701x stores data to SDT(out) with SSEF = 0. SDT load wait enable bit * 0: Does not use load wait function. * 1: Uses load wait function. Inserts wait cycles when PD7701x loads data from SDT(in) with SLEF = 0. Serial input continuous mode setting flag * 0: Enters single serial input mode after completion of current serial input. * 1: Enters serial input continuous mode to start serial input. Single serial input enable flag * 1: Starts serial input processing in single serial input mode (only once). SIEF flag set to 1 is automatically reset in next instruction cycle. Reserved bits * Value cannot be set to these bits. * Undefined when read. SDT store error flag * 0: No error * 1: Error (Set to 1 when PD7701x stores data to SDT(out) with SSEF = 0.) * Once set, this flag does not change its status until 0 is written by PD7701x. SDT load error flag * 0: No error * 1: Error (Set to 1 when PD7701x loads data from SDT(in) with SLEF = 0.) * Once set, this flag does not change its status until 0 is written by PD7701x. SDT store enable flag * Set to 1 when contents of SDT(out) is transferred to serial output shift register. * Cleared to 0 when PD7701x stores data to SDT(out). SDT load enable flag * Set to 1 when contents of serial input shift register is transferred to SDT(in). * Cleared to 0 when PD7701x loads data from SDT(in).
14
SITF
L/S
13
SOBL
L/S
12
SIBL
L/S
11
SSWE
L/S
10
SLWE
L/S
9
SICMNote
L/S
8
SIEFNote
L/S
7-4
Reserved
--
3
SSER
L/S
2
SLER
L/S
1
SSEF
L
0
SLEF
L
Note
Table 3-31 shows an example of combination of SICM and SIEF. When continuous data such as speech data is input, use status 2 (SICM = 1, SIEF = 0).
Remark The SST setting after hardware reset Initial SST after reset: 0x0002; * 16 bits input/output word length * MSB-first for input and output * No store/load wait function * No serial input continuous mode * Serial input not enabled
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Table 3-31. Combination of SICM and SIEF Bits
Example of combination 1 Bit 9 0 Bit 8 0 Function * Status transition mode. This mode is also set when serial input is not performed. * SIAK goes low. Even if this mode is set if SIAK is high, SIAK remains high until serial input is started. 2 1 0 * Continuous serial input mode. * SIAK outputs high level if serial input can be executed. After serial input has been started, SIAK goes low. Serial input is enabled again when SDT (in) is loaded, and SIAK outputs high level. If SDT(in) is empty, when a complete data word has been shifted in, the contents of SIS is transferred immediately (in synchronization with the SCK) to SDT(in) and SIAK goes high. Refer to Figure 3-55 (a). 3 0 1 * Single serial input mode. * SIAK outputs high level if serial input can be executed. After serial input has been started, SIAK goes low. SIAK remains low level even if SDT is loaded. * SIEF flag set to 1 is automatically reset in next instruction cycle. Refer to Figure 3-55 (b). 4 1 1 * The setting of this combination is prohibited.
SICM SIEF
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(3) Timing of serial interface
(a) Serial output timing Generally, serial output is performed in the following steps. Operations in steps <1> through <6> without SDT store wait cycles are illustrated in Figure 3-54 (a) and (b) for continuous and non-continuous data, respectively.
<1> <2>
The application program executes a store to SDT (serial data register). Consequently, the SDT store enable flag (SSEF) of the serial status register (SST) is cleared to 0, notifying the application program that no more data must be written to SDT. If the SDT store wait enable bit (SSWE) is set, the SDT store wait function is validated, automatically blocking a write access to SDT.
<3>
If the serial output shift register (SOS) is empty, the data set to SDT is transferred to SOS after 3 SCK cycles. The serial output request pin (SORQ) becomes active (high), informing an external device of issuance of a serial output request.
<4>
When the external device makes the serial output enable pin (SOEN) active (high level) (a), this pin is sampled at the falling edge of the serial clock pin (SCK) immediately afterNote 1 (b), at the next rising edge of SCK, SORQ becomes low (c) and data output to the serial data output pin (SO) is started (d).
<5>
After SDT has become empty, SSEF is set to 1, notifying the application program that the next data can be written (a), the SDT store wait function, which has been validated with SSWE = 1, is invalidated. At this time, an interrupt request is generated by SO (b). However, the interrupt is serviced as a valid interrupt or is recorded, depending on the status of the corresponding interrupt enable flag and EI status (refer to 3.4.4 "Interrupt").
<6>
If the next data is not supplied when the output of the last bit data has been completed, SO goes into a high-impedance state at the next rising edge of the SCKNote 2.
Notes 1. Before SOEN becomes active, SCK must rise at least three times. Bear this in mind especially in a system configuration where the clock is used in burst mode for only inputting/outputting data. 2. Under the following conditions, SO does not go into a high-impedance state but successively outputs the next data: if the next data has been already supplied before the last bit is output, and if SOEN becomes active before falling of SCK in the last bit output cycle and is sampled as valid (refer to Figure 3-54 (a)). After the last bit has been output, the rising edge of SCK must be supplied at least once.
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Figure 3-54. Serial Interface Output timing (a) Continuous data
<4>(c) <4>(c)
SCK (Input)
<4>(b) <4>(a) <4>(b)
SOEN (Input)
<3> <3>
SORQ (Output)
<5>(a) <5>(a)
SSEF (Status)
<2> <4>(d) <2> <4>(d)
SO (Output)
Hi-z
3 x system clock
1
2
3
4
5
7/15 8/16 1
2
3
4
5
7/15 8/16
Hi-z
<6>
1st data (8 or 16 bits)
4 x system clock
2nd data (8 or 16 bits)
4 x system clock
3 x SCK
Start condition: SOS empty, SDT empty
Store to SDT Store to SDT SDT SOS (2nd data) (1st data) (1st data) <1> SDT SOS <1> Serial output interrupt (2nd data) (For 2nd data)
<5>(b)
Serial output interrupt (For 3rd data)
<5>(b) 3 x system clock
(b) Non-continuous data
<4>(c)
SCK (Input)
<4>(b) <4>(a)
SOEN (Input)
<3>
SORQ (Output)
<5>(a)
SSEF (Status)
<2> <4>(d) <2>
SO (Output)
Hi-z
3 x system clock
1
2
3
4
5
7/15 8/16
Hi-z
<6>
1st data (8 or 16 bits)
4 x system clock
3 x SCK Store to SDT SDT SOS (1st data) (1st data)
<1> Start condition: SOS empty, SDT empty
Serial output interrupt (For 2nd data)
<5>(b)
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(b) Timing of serial input Generally, serial input is performed in the following steps. Operations in steps <1> through <4> without SDT load wait cycles are illustrated in Figure 3-55 (a) and (b). Figure 3-55 (a) and (b) show operations of steps <1> through <4> for input mode of continuous and single, respectively.
<1> Serial data input sequence is started when an external device makes the serial input enable pin (SIEN) active (high level) with the serial input enable (SIAK) pin being active (high level). <2> Changes in SIEN in <1> are sampled at the falling edge of SCK immediately afterNote 1 (a), SIAK goes low at the next rising edge of SCK (b), and inputting data given to the serial data input pin (SI) is started from the falling edge of the same SCK cycle (c). The data is loaded from the SI pin to the serial input shift register (SIS) bit by bit in synchronization with the falling edge of SCK. <3> SIAK becomes active (a) in synchronization with the rising edge of the SCK cycle, in which the last bit of the specified number of bits is loaded, immediately before the loading, informing the external device that the next data can be input. When the last bit has been loadedNote 2 (b) and if the SDT load enable flag (SLEF) is 0, the loaded bit is immediately transferred from SIS to SDTNote 3. After that, SLEF changes to 1, informing the application program that the serial input data word has been completed (c). If the data wait status is set with the SDT load wait enable bit (SLWE) set to 1, the wait function is released. Although an interrupt request is generated by SI (d) at this time, the interrupt is serviced as a valid interrupt or is recorded, depending on the statuses of the corresponding interrupt enable flags and the EI bit (refer to 3.4.4 "Interrupt"). <4> When the application program executes a load from SDT (a), SLEF is cleared to 0, indicating that the input data is empty (b). If SLWE is 1 at this time, the SDT load wait function is validated, automatically blocking further read access to SDT.
Notes 1. Before SIEN becomes active, SCK must rise at least three times. The hardware of the serial input/ output block performs a pipeline operation with SCK used as a timing clock. Bear this in mind especially in a system configuration where the clock is used in burst mode for only inputting/outputting data. With a system configuration where the clock is successively supplied, exercise care in respect to the first data after reset. After the last bit has been output, the rising edge of SCK must be supplied at least two times. 2. If SIEN becomes active and sampled as valid before SCK falls in the last bit input cycle, the next data is loaded from the successive next SCK cycle (refer to Figure 3-55). 3. SDTs are used separately for serial input and serial output.
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Figure 3-55. Serial Interface Input timing (a) SICM = 1, SIEF = 0; Continuous mode
SCK (Input)
<2>(a) <2>(c) <1> <3>(b)
SIEN (Input)
<3>(a)
SIAK (Output)
<2>(b)
SLEF (Status)
<4>(b)
SI (Input)
1
2
3
4
5
7/15 8/16 1
2
3
4
5
7/15 8/16
1st data (8 or 16 bits) 3 x SCK SICM=1, SIEF=0
(SST Reg.) Start condition: SIS empty, SDT empty 3 x system clock
2nd data (8 or 16 bits)
4 x system clock
SIS SDT (1st data)
<3>(c)
Load from SDT (1st data)
<4>(a)
3 x system clock
Serial input interrupt (1st data)
<3>(d)
SIS SDT (2nd data)
(b) SICM = 0, SIEF = 1; Single mode
SCK (Input)
<2>(a)<2>(c) <1>
SIEN (Input)
SIAK (Output)
<2>(b)
SLEF (Status)
<4>(b)
SI (Input)
1
2
3
4
5
7/15 8/16
3 x SCK SICM=0, SIEF=1
(SST Reg.) Start condition: SIS empty, SDT empty
1st data (8 or 16 bits) 3 x system clock SIS SDT (1st data)
<3>(c)
4 x system clock Load from SDT (1st data)
<4>(a)
Serial input interrupt (1st data)
<3>(d)
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(c) I/O timing of non-standard serial clock
Figure 3-56 shows the operation of the serial clock counter which are caused by non-standard serial clock.
Figure 3-56. Serial Interfaces - Operation of the Serial Clock Counter
One serial clock lost: SCK (Input)
8 1 2 3 7 8 1 2 7 8 1 2 7 8 1 2
SIAK (Output) SIEN (Input) SCK Counter -1 6 6 52 1 0 -1 -1 -1 -1 6 5 1 0 -1 6 5
incorrect input data Spike on serial clock: SCK (Input)
8 1 2 3 7 8 1
input data lost
correct input data
2
7
8
1
2
7
8
1
2
SIAK (Output) SIEN (Input) SCK Counter -1 6 54 3 0 -1 -1 6 5 1 0 -1 6 5 1 0 -1 6 5
incorrect input data
correct input data
correct input data
Condition for counter to start down-count: SIAK=1 and SIEN=1 at falling edge of SCK
Data can be input/output even when SIEN and SOEN are active. If a bit shift occurs, however, the I/O timing cannot be corrected because a non-standard serial clock is input. By deasserting SIEN and SOEN inactive, this bit shift can be corrected as shown above. In the above example, SIEN is input by counting SCK. However, it is more accurate if SIEN is input depending on the status of SIAK.
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(4) Handshake
There are three means to handshake with the serial interface of the PD7701x family, which can be implemented by application programs: * Polling * Wait * Interrupt Each format is described next. (a) Polling Synchronization of handshaking is established by always monitoring and evaluating the SDT store enable flag (SSEF) and SDT load enable flag (SLEF) of the serial status register (SST). Here is an example of serial output by means of polling:
/* Explicitly define SST1 and SO1 because they are not reserved words. */ #define SST1 0x3801 #define SO1 0x3800
/*Disable internal interrupts SO1 and SI1.*/ R0L = SR R0 = R1 | 0x0030 SR = R0L ; ; ;
R0L = 0x0 *SST1:X = R0L
; Set serial status as follows: ; * MSB first output ; * MSB first input ; * 16-bit word output ; * 16-bit word input ; * SDT store wait function is not used. ; * SDT load wait function is not used. ; * Serial input is not performed. ; * Clear serial input/output error ; flag.
POLL: R0L = *SST1:X ; Judge SSEF and loop to wait until ; store is enabled. R0 = R0 & 0x2 ;
if (R0 == 0)jmp POLL ;
*SO1:X = R1H
; Data of R1H is output because store is enabled.
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(b) Wait Under the following conditions, execution of data exchanges with the SDT(in) and/or SDT(out) registers cause instruction wait cycles: * when the store wait function is enabled (SSWE = 1) and a store to SDT(out) for serial output is to be executed, while SSEF = 0 (valid data exists in SDT(out)). * when the load wait function is enabled (SLWE = 1) and a load from SDT(in) for serial input is to be executed, while SLEF = 0 (valid data does not exist in SDT(in)). The advantage of this format is that describing handshake procedures in the application program is not needed, because the handshake procedure is automatically executed by hardware. Here is an example of serial output by using the wait function:
/* Explicitly define SST1 and SO1 because they are not reserved words. */ #define SST1 0x3801 #define SO1 0x3800
/* Disable internal interrupts SO1 and SI1. */ R0L = SR ; R0 = R0 | 0x0030 ; SR = R0L ; R0L = 0x800 *SST1:X = R0L ; Set serial interface as follows: ; * MSB first output ; * MSB first input ; * 16-bit word output ; * 16-bit word input ; * SDT store wait function is used. ; * SDT load wait function is not used. ; * Serial input is not performed. ; * Clear serial input/output error flag. ; Data of R1H is output as soon as ; SSEF = 1.
*SO1:X = R1H
Caution
When data is written from the application program to SDT, the wait is not released unless SDT is transferred to SOS (i.e., unless all the bits of the previous data of SOS are shifted out to the external device). If internal writing of DSP and external reading do not correspond on a one-toone basis vis-a-vis SDT, a hang-up may occur. During wait, interrupts are delayed (refer to secton 3.4.4 "Interrupt").
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(c) Interrupt Handshaking is established by interrupts, if data can be stored to SDT (out) and data can be loaded from SDT (in). Therefore, the advantage of this format is that, even while other processing is under execution, serial input/output can be executed independently (asynchronously) of the processing. Here is an example of serial input/output using an interrupt:
/* definition of serial I/O register names #define SST1 *0x3801:X #define SI1 *0x3800:X #define SO1 *0x3800:X /* interrupt vector table entries SegSI1 IMSEG AT 0x220 R0H = SI1 R0 = R0H*R1H *DP0++ = R0H RETI SegSO1 IMSEG AT 0x224 R0H = *DP4++ SO1 = R0H RETI NOP
*/
*/
; sio#1 input interrupt routine : load from SDT (in) ; ; save to buffer ; return from interrupt ; sio#1 output interrupt routine ; read from buffer ; save to SDT(out) ; return from interrupt ;
/* disable interrupts to initialize serial input/output */ R1L = EIR ; disable interrupts generally R1 = R1 | 0x8000 ; EI = 1 EIR = R1L ; NOP ; wait 2 cycles until NOP ; EI = 1 effective R0L = SR ; enable SI1 and SO1 interrupts R0 = R0 & 0xFFCF ; SR = R0L ; R1 = R1 & 0x7FFF ; enable interrupts generally EIR = R1L ; FINT ; discard all pervious interrupts ; ; ; ; ; initialize SST1 input/output: MSB-first, 16-bit no load/store wait function serial input continuous mode dummy store (see below)
R0L = 0x0200 SST1 = R0L SO1 = R0L
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Cautions
Note the following points when executing serial output interrupt because the interrupt occurs after data has been transferred from the SDT register to the serial output shift register: (1) Transfer first dummy data and then forcibly generate an interrupt, or do not use interrupts during the transfer of the first data. (2) When transferring data in burst mode, first disable interrupts immediately before the instruction which transfers the last word to SDT, then execute the instruction introduced in (1) after the completion of the next burst data preparation, to transfer the next burst data. This is because the first word of data to be burst-transferred may not be completely prepared if an interrupt is generated during the transfer of the last burst data word.
Example: R0L = SR R0 = R0 | 0x0020 SR = R0L *SO1: X = R0H ; /* When last word is stored to SDT. */ ; /* (DI status during interrupt processing) */ ; /* SO1 interrupt is disabled. */ ; ;
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3.7.4 Host interface
The PD7701x family is provided with a host interface that transfers data with an external host CPU and DMA controller. The features of this host interface are as follows:
* 8-bit parallel port * Data range Higher 8 or lower 8 bits are selected by address. * Internal data bus connection Connected to X and Y buses. * Internal 16-bit, external 8-bit configuration External device is interfaced through 8-bit data bus. * Internal handshake Handshake by means of polling, wait, or interrupt * External handshake Handshake by means of dedicated status signal.
A host interface control circuit (HCTL) controls the pins and registers. Figure 3-57 shows the block diagram of the host interface.
Figure 3-57. Host Interface
Peripheral bus (16 bits) 16 16 16
HDT (in)
HDT (out)
HST
8
HCTL
HD0-HD7
HA0
HA1
HCS
HRD
HWR
HRE
HWE
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[Operational outline of host interface] This section explains the internal logical operation of the host interface of the PD7701x family (for the detailed timing, refer to Figures 3-59 and 3-60). One buffer stage is provided for both input and output to transfer data via host interface. Host input is performed by using the following registers: * HDT (in) register (host data input register): Inputs 8-bit parallel data (higher byte and lower byte) from the HD0 through HD7 pins, and output 16-bit parallel data to the peripheral bus. Host output is performed by using the following registers: * HDT (out) register (host data output register): Writes 16-bit parallel data from the peripheral bus and outputs 8-bit parallel data (higher byte and lower byte) from the HD0 through HD7 pins. The host interface can be accessed from the external device by using 8 bits of host data I/O pins. Internally, the interface can be accessed by using the parallel input register HDT (in) and output register HDT (out). To establish synchronization for host data transfer, the following internal flags are provided to monitor the status of the dedicated external pins and registers. * HWE (host write enable), HWEF (host write enable flag): These are an external pin and a flag (flag of the host status register) that monitor the status of HDT (in). HWE = high level, HWEF = 0 (HDT (in) is not empty.) The PD7701x can load data from HDT (in). HWE = low level, HWEF = 1 (HDT (in) is empty.) The host can write new data to HDT (in). The PD7701x cannot load data from HDT (in). * HRE (host read enable), HREF (host read enable flag): These are an external pin and a flag (flag of the host status register) that monitors the status of HDT (out). HRE = high level, HREF = 0 (HDT (out) is empty.) Valid data does not exist in HDT (out). The host can read data from HDT (out). The PD7701x can store output data to the HDT (out). HRE = low level, HREF = 1 (HDT (out) is not empty.) The host can read new data from HDT (out). The PD7701x can store output data to HDT (out).
Valid data still exists in HDT (in). The host cannot write new data to HDT (in).
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Table 3-32. Status Indicators of Host Read/write Interface
Register Host write HDT(in) Status indicator HWE pin Status Comments
High: Not empty Host cannot write to HDT(in) Low: Empty Host can write to HDT(in) Data cannot be loaded from HDT (in)
HWEF flag
1: 0:
Empty
Not empty Data can be loaded from HDT(in) No new data in HDT(out) to be read by host
Host read HDT(out) HRE pin
High: Empty
Low: Not empty Host can read data from HDT(out) HREF flag 1: 0: Not empty Data cannot be stored to HDT(out) Empty Data can be stored to HDT(out)
Figure 3-58. Function Diagram of Host Interface
Peripheral bus (16 bits) Load 16 INT 16 bit 1 bit 0
HREF HWEF
HST Reg.
Store 16 INT
************************
HDT (in) 8 8 8 8 8 switch from HD0-HD7 to the busses
HDT (out) 8
8
HWE HA1 HA0 HCS HRD HWR
HD0-HD7
HRE
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(1) Pins of host interface
All control pins of the host interface are active-low. (a) HCS (Host Chip Select - input) This pin inputs a host interface select signal. This signal is active (low) while the host CPU accesses a register of the host interface. (b) HA1 and HA0 (Host Addresses 1 and 0 - input) These pins input an address of the host interface. They specify a register of the host interface to be accessed. Do not change the statuses of these pins while the host CPU is accessing a register of the host interface. (c) HRD (Host Read strobe - input) This pin inputs the read strobe signal of the host interface. It becomes active (low) when the host CPU reads the data of a register of the host interface. This signal must not be active concurrently with the HWR signal. (d) HWR (Host Write strobe - input) This pin inputs the write strobe signal of the host interface. It becomes active (low level) when the host CPU writes data to a register of the host interface. This signal must not be active concurrently with the HRD signal. (e) HD0-HD7 (Host Data 0-7 - input/output) These pins input or output data to or from the host interface. Data is input or output when the host CPU accesses a register of the host interface. These pins go into a high-impedance state when HCS is inactive (high). (f) HRE (Host Read Enable - output) This pin outputs a signal indicating that HDT is enabled to be read. It is asserted active (low level) if HDT is enabled to be read and is deasserted inactive (high level) at the falling edge of the HRD pin when the higher byte of the data of HDT is read. This pin remains unchanged even if the lower byte of HDT is accessed. This pin is deasserted inactive at hardware reset. (g) HWE (Host Write Enable - output) This pin outputs a signal indicating that HDT is enabled to be written. It is asserted active (low level) if HDT is enabled to be written and is deasserted inactive (high level) at the falling edge of the HWR pin when data is written to the higher byte of HDT. This pin remains unchanged even if the data of the lower byte of HDT is accessed. This pin is deasserted inactive at hardware reset.
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Table 3-33. Pins Status during and after Hardware Reset
Pin HCS HA0, HA1 HRD HWR HD0-HD7 HRE HWE I/O I I I I I/O O O H H During reset -- -- -- -- Initial after reset -- -- -- -- Hi-Z (when HCS pin is inactive) H H
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(2) Registers of host interface
(a) Host data register (HDT-0x3806:X/:Y) This 16-bit register is used to input or output data to or from the host interface. Data can be stored to and loaded from HDT by use of load/store instructions. <1> Host data output register This 16-bit register sets data to be output from the host interface. When a store to HDT is executed, data is input to this register through the peripheral bus. When data is read by an external device, the higher or lower 8 bits are specified by HA0. <2> Host data input register This 16-bit register sets the data to be input from the host interface. When a load from HDT is executed, the data of this register is output to the peripheral bus. When data is written by an external device, the higher or lower 8 bits are specified by HA0.
(b) Host interface status register (HST-0x3807:X/:Y) Host interface status register HST is a 16-bit register that indicates the mode setting and status of the host interface. It indicates the specification, and write or read error between the host CPU and host interface and between the host interface and PD7701x. Data can be input to or output from HST by using a load/store instruction. When the value of this register is read by the external device, the higher 8 bits or lower 8 bits are specified by HA0. The value of HST is set to 0x0301 at reset. Table 3-34 shows the function of each bit of HST, and Table 3-35 shows the set condition of the host I/O error flags.
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Table 3-34. Function of HST (0x3807:X/:Y)
Bit 15-11 Name Reserved R/W from host -- Load/Store from Bit function Reserved bits * No value can be set to these bits. * These bits are undefined when read. HDT access wait enable bit * 0: Wait is not used * 1: Wait is used Wait cycles are inserted if the PD7701x attempts to store data to HDT (out) while HREF=1, or to load data from HDT (in) while HWE=1. HRE mask bit * 0: Does not mask. HRE changes according to the HREF status (refer to below). * 1: Masks HRE becomes inactive (high level). HWE mask bit * 0: Does not mask. HWE changes according to the HWEF status (refer to below). * 1: Masks HWE becomes inactive (high level). User's flag User's flag Host read error flag * 0: No error * 1: Error Set to 1 when host CPU reads HDT when HREF is 0. * Once set to 1, it does not change until 0 is written by program. Host write error flag * 0: No error * 1: Error Set to 1 when host CPU writes HDT when HWER is 0. * Once set to 1, it does not change until 0 is written by program. HDT store error flag * 0: No error * 1: Error Set to 1 when PD7701x store to HDT when HREF is 1. * Once set to 1, it does not change until 0 is written by program. HDT load error flag * 0: No error * 1: Error Set to 1 when PD7701x loads from HDT when HWEF is 1. * Once set to 1, it does not change until 0 is written by program. Host read enable flag * 0: Read disabled * 1: Read enabled Set to 1 when the PD7701x stores data to HDT. Cleared to 0 when host CPU reads higher byte of HDT. * Ignored when written. Host write enable flag * 0: Write disabled * 1: Write enabled Set to 1 when the PD7701x loads data to HDT. Cleared to 0 when host CPU writes higher byte of host CPU. * Ignored when written.
PD7701x
--
10
HAWE
R
Load/Store
9
HREM
R
Load/Store
8
HWEM
R
Load/Store
7 6 5
UF1 UF0 HRER
R R R
Load/Store Load/Store Load/Store
4
HWER
R
Load/Store
3
HSER
R
Load/Store
2
HLER
R
Load/Store
1
HREF
R
Load
0
HWEF
R
Load
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Remark The HST setting after hardware reset: initial HST after reset: 0x0301: * no wait function * HRE/HWE mask: Masked * host write enabled * host read disabled
Table 3-35. Conditions of Host Input/Output Error Flags Settings
Error flag HRER HWER HSER HLER Set condition Host read while HREF=0 Host write while HWEF=0 Store to HDT while HREF=1 Load from HDT while HWEF=1 Reset condition by hardware reset or by program
(3) Registers of host interface when viewed from host
The host CPU specifies the higher or lower bytes of either the host status register HST or host data register HDT by use of the HA0 and HA1 inputs. Table 3-36 shows the registers of the host interface when they are accessed by an external device.
Table 3-36. Selecting Host Interface Registers
HCS 0 0 0 0 0 0 0 0 0 1 HRD HWR HA1 0 0 0 0 0 1 1 1 1 x 0 1 1 1 1 0 0 0 1 x x 0 0 1 1 0 0 1 x x HA0 x 0 1 0 1 0 1 x x x Register subject to transfer Disabled HDT (output) HDT (output) HST HST HDT (input) HDT (input) Disabled No register No register Byte -- Lower 8 bits Higher 8 bits Lower 8 bits Higher 8 bits Lower 8 bits Higher 8 bits -- -- --
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(4) Timing of host interface
(a) Host read operation (PD7701x --> host) Data is transferred from the PD7701x to the host in the following steps. Figure 3-59 shows reading operations of 16-bit data to HDT without wait cycles.
<1> The application program of the PD7701x stores data to the host data register (HDT) (a), (b). <2> Consequently, the host read enable flag (HREF) of the host interface status register (HST) is set to 1 (a). If the HRE mask bit (HREM) of HST is 0, the HRE pin becomes active (low), and is output to external devices as a hardware signal (b). <3> The host can recognize that data is present in HDT by any of the following methods: (1) Reads HST and detects HREF = 1 by software (a), or (2) Detects the low level of the HRE pin (b). <4> The host reads HDT. If 16-bit data is transferred at this time, the lower 8 bits (a) and then the higher 8 bits (b) must be read in this order. If 8-bit data is transferred, the higher 8 bits are always read (refer to the logic of HREF and HRE). <5> HREF of HST is cleared to 0 after step <4> (b), and the HRE pin becomes inactive (high) in step <4> (b). At this time, an interrupt request is generated by HO (c). This interrupt is processed as a valid interrupt or is recorded depending on the status of the corresponding interrupt enable flag and EI status (refer to 3.4.4 "Interrupt").
Figure 3-59. Host Read Sequence (PD7701x --> host): HDT read without wait
Instruction execution <1> (a) HDT data <1> (b) HDT Empty Data <2> (a) HREF <3> (a) <5> (a)
HRE
<2> (b)
<3> (b) <4>
<5> (b)
Host operation
Read HDT <4> (a) <4> (b) Higher 8 bits <5> (c)
HRD Lower 8 bits HO INT
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(b) Host write operation (PD7701x <-- host) Data is transferred from the host to the PD7701x in the following steps. Figure 3-60 shows examples of writing HDT without wait cycles when 16-bit data is transferred.
<1> The host writes data to the HDT of the PD7701x. If 16-bit data is transferred at this time, the lower 8 bits (a) and the higher 8 bits (b) are written in this order; if 8bit data is transferred, data is always written to the higher 8 bits of HDT (refer to the logic of HWEF and HWE). <2> Consequently, HWEF of HST is cleared to 0, informing the application program of the PD7701x that data has been written to HDT (a). The HWE pin becomes inactive (high level in step (b)), informing an external device that HDT is busy (b). An interrupt request is also generated by HI (c). Whether this interrupt is processed as a valid interrupt or is recorded depends on the status of the corresponding interrupt request flag or EI status (refer to 3.4.4 "Interrupt"). <3> The application program of the PD7701x can recognize that HDT is ready with the data from the host by either of the following methods: (1) by detecting 0 of HWEF of HST (a), or (2) by waiting for interrupt caused by HI (b). <4> Consequently, the application program loads from HDT (a). As a result of the load, HWEF is set to 1 (b). At the same time, the HWE pin becomes active (low) (c), and the external circuit recognizes that HDT is enabled to write.
Figure 3-60. Host Write Sequence (PD7701x <-- host): HDT write without wait
<1> Host operation Write data <1> (a) HWR Lower 8 bits HDT Empty Higher 8 bits Lower <2> (a) HWEF <2> (b) HWE Instruction execution <2> (c) HI INT <3> (b) <4> (a) Load HDT <3> (a) <4> (c) Completed data Empty <4> (b) <1> (b)
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(5) Handshake
Handshaking between the PD7701x and host can be established by: * Polling * Wait * Interrupt Each mode is described next. (a) Polling Synchronization of handshaking is established by always monitoring and evaluating the host read enable flag (HREF) and host write enable flag (HWEF) of the host interface status register (HST). Here is an example of host read (PD7701x --> host) by means of polling:
/* Explicitly define HST and HDO because they are not reserved words. */ #define HST 0x3807 #define HDO 0x3806 /*Disable internal interrupts HO and HI.*/ R0L = SR R0 = R0 | 0x0300 SR = R0L R0L = 0x0 *HST:X = R0L ; ; ; ; Set host status as follows: ; * Does not use HDT access wait ; function. ; * Does not mask HRE function. ; * Does not mask HWE function. ; * Clears all user flags. ; * Clears all error flags. POLL: R0L = *HST:X R0=R0 & 0x2 ; Judges HREF and loops to wait ; until host reads HDT. ; if (R0! = 0)jmp POLL ; *HDO:X = R1H ; Data of R1H is output because HDT ; has become empty.
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(b) Wait Under the following conditions, execution of data exchanges with the HDT(in) and/or HDT(out) registers cause instruction wait cycles: * when the load/store wait function is enabled (HAWE=1) and a store to HDT(out) is to be executed, while HREF=1 (valid data exists in HDT(out)) * when the load/store wait function is enabled (HAWE=1) and a load from HDT(in) is to be executed, while HWEF=1 (valid data does not exists in HDT(in)) Therefore, the advantage of this format is that writing handshake procedures is not required in application program, because the handshake procedure is automatically executed by hardware. Here is an example of host read by using the wait function:
/*Explicitly define HST and HDO because they are not reserved words.*/ #define HST 0x3807 #define HDO 0x3806
/Disable internal interrupts HO and HI.*/ R0L = SR R0 = R0 | 0x0300 SR = R0L ; ; ;
R0L = 0x0400 *HST:X = R0L
; Set host status as follows: ; * Uses HDT access wait function. ; * Does not mask HRE function. ; * Does not mask HWE function. ; * Clears all user flags. ; * Clears all error flags.
*HDO:X = R1H
; Outputs data of R1H.
If HDT is
; busy, wait cycle is inserted.
Caution
When data is written from the application program to HDT, the wait is not released unless HDT is read by the external device. If internal writing of DSP and external reading do not correspond on a one-to-one basis vis-a-vis HDT, a hang-up may occur. During wait, interrupts are delayed (refer to section 3.4.4 "Interrupt").
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(c) Interrupts Handshaking can be established by generating an interrupt, if data can be stored to HDT (out) or loaded from HDT (in) by the PD7701x. Therefore, the advantage of this format is that host input/output can be executed independently (asynchronously) of the other processing even while other processing is under execution. Here is an example of host input/output using an interrupt:
/ * Define host I/O */ #define HST * 0x3807: X #define HDO * 0x3806: X #define HDI * 0x3806: X /* Entry of interrupt vector table */ SegHi IMSEG AT 0x230 R0H = HDI *DP0++ = R0H RETI NOP SegHo IMSEG AT 0x234 R0H = *dp4++ HDO = R0H RETI NOP ; hio input interrupt routine ; Read from HDT (in) ; Saves to buffer ; Returns from interrupt ; ; hio output interrupt routine ; Reads from buffer ; Writes to HDT (out) ; Returns from interrupt ;
/* Disables interrupts to initialize host I/O */ R1L = EIR R1 = R1 | 0x8000 EIR = R1L NOP NOP R0L = SR R0 = R0&0xFCFF SR = R0L R1 = R1&0x7FFF EIR = R1L FINT ; Disables all interrupts ; EI = 1 ; ; Two wait cycles are necessary until EI = 1 ; becomes valid ; Enables HI and HO interrupts ; ; ; Enables all interrupts ; ; Discards previous interrupt ; Initializes HDT R0L = 0x0 HST = R0L HD0 = R0L ; Without HDT access wait function ; No HRE, HWE mask. Clears user flag ; Dummy store (Refer to "Caution" below)
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Caution
Because the host output interrupt occurs at the rising edge of the HRD pin when the higher byte of the HDT register is accessed, the following points must be noted. (1) Transfer the first data by forcibly generating an interrupt by transferring dummy data or by transferring data without using an interrupt. (2) If data is transferred in the burst mode, the chances are that the first data for the next burst transfer is not generated if an interrupt occurs at the last word of the burst data. Therefore, disable the interrupt by the instruction immediately before the one that transfers the last word to HDT, execute the same instruction as (1) after generation of the next burst data has been completed, and transfer the next burst data.
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3.7.5 General-purpose input/output port
The PD7701x is provided with a 4-pin input/output port. The following are the features of this port.
* Set in the input mode at hardware reset, and the values input to P0 and P1 after reset determine the boot mode. * Each pin can be set in the input or output mode by the application program. * The output value of the pin set in the output mode can be controlled independently.
Figure 3-61. General-purpose Input/Output Port
Peripheral bus (16 bits) Load 4 PDT (in) 4 4 Store 16 Bit manipulation PCD
PDT (out) 4 Set mode x4 4 P0-P3
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(1) Usage of the general-purpose port
There are three methods for using general-purpose port. (a) Mode change (input --> output, output --> input) The port command register PCD is used to set the port pins P0-P3 in the input or output mode.
store to PCD
******
* set the mode of each bit (input or output)
(b) Input data (P0-P3 --> PD7701x) Input data is loaded from the port data register PDT(in).
load from PDT
******
* input the 4-bit data
(c) Output data (P0-P3 <-- PD7701x) There are two methods for setting an output port pin to a defined status. (i) using PDT Output data is stored to the port data register PDT(out).
store to PDT
*******
* output the 4-bit data
(ii) using PCD The status of a single output port pin can be manipulated by the port command register PCD. Mode setting and bit manipulation can be set concurrently.
store to PCD
******
* set the mode of each bit (input or output) * manipulate the 1-bit output data (low or high)
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(2) Pins of port interface
(a) P0-P3 (general-purpose input/output port) These are general-purpose input/output pins and have the following functions: * The output pin status is changed in synchronization with the rising edge of CLKOUT. * The input pin is sampled in synchronization with the rising edge of CLKOUT.
(3) Port-related registers
(a) Port data register (PDT-0x3804:X/:Y) This 16-bit register transfers data by using the general-purpose input/output port. To input data from the general-purpose input/output port, a load from PDT is performed. To output data, the data is stored to PDT whose value is then set to P0-P3. These pins correspond to the bit 0 to bit 3 of PDT. Data can be exchanged with the PDT register by use of load/store instructions. When a load from PDT is executed, the data of this register is output to the peripheral bus. In input mode, the bit n of the PDT is set to 1 when high is input to the Pn pin, cleared to 0 for a low level input; if the Pn' is an output pin, the value of bit n' is undefined when load from PDT is performed, where n and n' are suffixes for correspondence indication and different numbers each other. When a store to PDT is executed, the data is input to this register from the peripheral bus. In output mode, the Pn' pin outputs high when the bit n' of the PDT is set to 1, and outputs a low for 0; if the Pn pin is an input pin, the bit n value does not affect the port pin. (b) Port command register (PCD-0x3805:X/:Y) This 16-bit register specifies the input or output direction of the general-purpose input/ output port, and bit manipulation of the output pins. Data can be exchanged with the PCD register by use of load/store instructions. Note that not all of the PCD register bits can be loaded to a general-purpose registers (refer to the following table). The value of PCD is cleared to 0 at reset. Table 3-37 shows the function of each bit of PCD.
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Table 3-37. Port Command Register (PCD - 0x3805:X/:Y)
Bit 15 Name BE Category Bit manipulation Load/Store Bit function (L/S) S Bit manipulation enable bit * 0: Does not manipulate bit. * 1: Manipulates bit Manipulation method is specified by B1, B0, and PSR. * Undefined when read. Port set/reset specification bit * 0: Reset (low level) * 1: Set (high level) * Manipulation port is specified by B1 and B0. * Valid when BE = 1. * Undefined when read. Mode setting enable bit * 0: Does not set mode. * 1: Sets mode. Contents to be set are specified by IO and M3-M0. * Undefined when read. Input/output specification bit * 0: Specifies input mode. * 1: Specifies output mode. * Port to be set is specified by M3-M0. * Valid when ME = 1. * Undefined when read. Reserved bits * No value can be set to these bits. * Undefined when read. Bit manipulation port specification bits * B1, B0 = 00:P0 01:P1 10:P2 11:P3 * Set/reset is specified by PSR. * Valid when BE = 1. * Undefined when read. Reserved bits * No value can be set to these bits. * Undefined when read. Mode setting port specification bits M3 = 0: P3 unselected, 1: P3 selected M2 = 0: P2 unselected, 1: P2 selected M1 = 0: P1 unselected, 1: P1 selected M0 = 0: P0 unselected, 1: P0 selected * Selection can be specified independently. Input/output mode status bits M3 = 0: P3 input mode, 1: P3 output mode M2 = 0: P2 input mode, 1: P2 output mode M1 = 0: P1 input mode, 1: P1 output mode M0 = 0: P0 input mode, 1: P0 output mode
14
PSR
Bit manipulation
S
13
ME
Mode setting
S
12
IO
Mode setting
S
11,10 Reserved --
--
9, 8
B1, B0
Bit manipulation
S
7-4
Reserved --
--
3-0
M3-M0
Mode setting
S
Mode status
L
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(4) Timing of port interface
The general-purpose I/O port is not assumed to be used synchronously, but is synchronized with the rising edge of CLKOUT during data input/output. (a) Mode change from input to output
System clock
Instruction
if id ie Store to PCD: input output
Input/output mode
Input
Output
Bit manipulation
Old data
Delay
New manipulated data
P0-P3
Input data
New manipulated data
The mode of each pin is changed from input to output two system clocks after the execution cycle of the instruction that stores data to the PCD register.
Example program: #define PCD=0x3805 #define PDT=0x3804 R1L=0x0000 *PDT:x=R1L R0L=0x3001 *PCD:x=R0L ; ; ; :
initialize PDT P0 --> output port
Caution
Because the PDT register is undefined after hardware reset, write data to the PDT register before storing data to the PCD register.
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(b) Mode change from output to input
System clock
Instruction
if
id
ie input if id ie
Store to PCD: output
Required 4 instruction cycles
Load from PDT (for input data 1) Input/output mode Output Input
Delay Input Input Input data 1 data 2 data 3
P0-P3
Output data
************************************
Input impossibility
The mode of each pin changes from output to input after two system clocks since execution cycle of store to PCD register, but the PD7701x inhibit the pin's data from being input during two system clocks after then. Therefore it is required that minimum 4 system clocks between store to PCD register and load from PDT register.
Example program: #define PCD=0x3805 #define PDT=0x3804 R0L=0x200f ; *PCD:x=R0L ; P0-P3 output --> input R1L=*PDT:x ; load from PDT
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(c) Timing of input ports
System clock
Instruction
if id ie Load from PDT (for input data 1)
PDT(in)
Input Input Input data 1 data 2 data 3
******************************************
Synchronize with system clock P0-P3
Input Input Input data 1 data 2 data 3
********************************************************
The pin's input data is loaded after synchronized with the rising edge of two system clocks. (d) Timing of output ports
System clock
Instruction
if
id
ie
Store to PDT if id ie
Store to PCD (bit manipulation)
PDT(out)
Data stored to PDT
Delay
Bit manipulated data
Delay
P0-P3
Data stored to PDT
Bit manipulated data
(In case of store to PDT register) The output data is output after one system clock since execution cycle of store to PDT register.
(In case of store to PCD register) The 1-bit manipulated data is output after two system clocks since execution cycle of store to PCD register.
Caution
If bit manipulation by the PCD register and data output by storing to the PDT register are executed at the same time, the data of the PDT register takes precedence over bit manipulation by the PCD register.
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(e) Output port setting (by use of PCD and PDT registers)
System clock
Instruction
if
id
ie
Store to PCD: bit manipulation
if
id
ie
Store to PDT: output data
Input/output mode
Input
Output
Bit manipulation
Old data
New manipulated data
PDT(out)
Old data
Delay
New data
P0-P3
Input data A
New data by PDT(out) New manipulated data
The manipulated data is output after two system clocks since execution cycle of store to PCD register. Next, when the output data is output after one system clock since execution cycle of store to PDT register, spike noise may occur at point A. Therefore it is required that minimum 1 system clock between store to PCD register and store to PDT register. Example program: #define PCD=0x3805 #define PDT=0x3804 R0L=0xf00f *PCD:x=R0L R1L=0x0000 *PDT:x=R1L ; ;P0-P3 input --> output, P0 --> high ; ;P0-P3 --> low
Cautions 1. If at least one system clock is not inserted between the instruction that stores data to the PCD register and the instruction that stores data to the PDT register, a spike may be generated at point A. 2. Because the value of the PDT register is undefined after hardware reset, set the PDT register before storing data to the PCD register.
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(4) Example of port programming
Here is an example of a program using the general-purpose input/output port. In this example, the following is executed: * P0 and P1 are set in the output mode. * P2 and P3 are set in the input mode. * P0 outputs a low level, and P1 outputs a high level.
Example of programming general-purpose input/output port
#define #define #define #define #define #define #define
PDT
0x3804
PCD 0x3805 All_In_mode 0x200F P0_Out_mode P1_Out_mode Out_P0_Low Out_P1_High 0x3001 0x3002 0x8000 0xC100 ; P3-P0 input pins ; P0 output pin (low level) ; P1 output pin (high level)
R0L = All_In_mode *PCD:x = R0L; R0L = P0_Out_mode+Out_P0_Low *PCD:x = R0L; R0L = P1_Out_mode+Out_P1_High *PCD:x = R0L;
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3.7.6 Wait controller
When the external memory area is accessed, the number of wait cycles to be inserted can be specified in advance by using a register. The main features of the wait controller are as follows:
* Independently controls the data memory space and instruction memory space. * Four types of wait cycles (0, 1, 3, and 7 wait cycles). * Can be used with the WAIT pin (data memory space).
Figure 3-62 shows the block diagram of the wait controller.
Figure 3-62. Wait Controller
Peripheral bus (16 bits) 16 16
DWTR
IWTR
WCTL
WAIT
(1) Data memory wait cycle register (DWTR-0x3808:X/:Y)
Refer to paragraph (d) "Wait controller" in section 3.5.2 (3).
(2) Instruction memory wait cycle register (IWTR-0x3809:X/:Y)
Refer to paragraphs (d) "External instruction memory interface" and (f) "Wait function for instruction memory access" in section 3.4.2 (1).
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3.7.7 Debug interface (JTAG)
The PD7701x family is provided with the following functions conforming to JTAG interface: * JTAG port * Boundary scan test function * Debug function (In-Circuit Emulation function)
(1) JTAG port
Joint Test Action Group (JTAG) is an organization founded to promote standardization of boundary scan, a technique to facilitate testing of printed wiring boards that are mounted in electronic systems, and a standardization plan by this organization is recommended as "IEEE1149.1." A device conforming to JTAG has an access port for testing, and the device can be tested independently of the internal logic. The PD7701x family is provided with a register and a control circuit for In-Circuit Emulation, in addition to the instruction register, bypass register, and boundary scan register, which are specified to be essential by the above recommendation. For the details of JTAG, refer to "IEEE1149.1."
[Debug pins (TAP: test access port)] Four pins and In-Circuit Emulation pin (TICE) conforming to the recommendation are provided. * TCK (input) ........... Test clock input pin. Input 0 when not used (conforms to recommendation). * TMS (input) ........... Test mode select input. Sampled at the rising edge of TCK. Internally pulled up. * TDI (input) ............ Test data input. Sampled at the rising edge of TCK. Internally pulled up. * TDO (output) ........ Test data output. Changes output in synchronization with the falling edge of TCK. * TICE (output) ........ Output to organize the break mode of In-Circuit Emulation.
Caution
Do not stop TCK while it is high.
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(2) Boundary scan test function
The boundary scan test method allows testing of the board level and chip level of the target system in a consistent test phase. This is why this method has been widely employed for automatic systems at many production sites. The PD7701x family has boundary scan functions as described below. (a) Test instruction register This 8-bit register is used to select test parameters and a test data register. Table 3-38 lists the supported instructions.
Table 3-38. Test Instructions
Bit 76543210 00000000 00000001 11111111 Instruction
EXTEST instruction SAMPLE/PRELOAD instruction BYPASS instruction
Caution The operation is undefined if data other than above is input.
(b) Test bypass register This register outputs the data input from TDI to TDO. Refer to BYPASS instruction in Table 3-38.
(3) Debug function (in-circuit emulator function)
The PD7701x family is provided with debug monitoring functions using JTAG with a runtime program. These functions have the following features:
* Break function * Break by fetch of specified instruction address * Break by reading/writing specified data memory address
* Non-break monitor function * References or changes the contents of a register or memory during program execution
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Cautions 1. Detailed operations of the debug function are not made public to users. 2. The debug function is used by the hardware debugger for the PD7701x family (IE-77016). Figure 3-64 shows the JTAG pin connections when the IE-77016 is used. When the IE-77016 is not required, connect these pins according to 2.4 "Handling of Unused Pins."
Figure 3-63. Appearance of JTAG Pins
(a) PD77016 (b) PD77015, 77017, 77018, 77018A, 77019
Figure 3-64. The JTAG Pin Processing (a) PD77016
10-pin header TMS 100
TDI
99
TCK
98
TICE
97
TDO
96
10 k
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(b) PD77015, 77017, 77018, 77018A, 77019
10-pin header TMS 92
TDI
91
TCK
90
TICE
89
TDO
88
10 k
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Chapter 4
Boot Function
This chapter explains the boot function of the PD7701x family. First, the functional outline is explained, and then the types of the boot function (modes), booting at reset, a boot subroutine, and the time required for booting are described in that order.
1 2 3 4 5 6 A B C
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4.1 General
4.1
General
The PD7701x family is provided with a program to be booted up to the internal instruction RAM. This program is stored in its internal ROM at addresses 0-0xFF of the instruction space. This program provides users with several subroutine services, including a reset boot function and a reboot function. The reset boot function enables execution of booting immediately after the hardware is reset and the program counter is cleared to "0". The reboot function allows users to rewrite program data in the RAM area of the instruction space from the application program. The subroutine entry points for using these functions are made public to users. This chapter describes boot modes (by classifying and comparing modes by aspect), the boot functions in each mode, boot parameters, and how to call boot subroutines. The following registers are used to execute booting: [Registers whose contents are affected by boot execution] * R7 * DP3 * DP7 * HDT (host data register) [Registers that are set before booting] * IWTR (instruction memory wait cycle register) * DWTR (data memory wait cycle register) * HST (host interface status register)
Caution
All the above registers are not always used depending on the selected boot mode. For details, refer to the description of each boot mode.
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4.2 Boot Modes
4.2
Boot Modes
4.2.1 Classification of boot modes
The boot modes can be classified according to the following three attributes: * Boot starting format (reset boot vs. reboot) * Boot source (self-boot vs. host boot) * Transfer word size (word boot vs. byte boot)
(1) Classification by boot starting format
Booting can be classified into the following two types according to the starting format: (a) Reset boot and (b) Reboot. (a) Reset boot Booting by resetting the PD7701x hardware is called reset boot. When the hardware is reset, the PC (program counter) is cleared to "0" indicating address 0 of the instruction memory. Because this address is allocated as the reset boot entry point provided in the internal boot ROM area, the PD7701x automatically executes booting. With the reset boot, the instruction memory area to be booted is limited to the internal instruction RAM (starting from address 0x200). (b) Reboot Booting by calling a boot servicing subroutine from an application program is called reboot. Some subroutine entry points for booting are provided in the boot ROM area and made public to users. By accessing these entry points from an application program, any part of the instruction RAM can be rewritten at any time. The reboot function is mainly used to load program data to the external instruction memory or to rewrite the contents of the external instruction memory with the PD77016.
(2) Classification by boot source
Booting consists in rewriting instructions in a certain format. The boot function can be classified into the following two types depending on from where the op code data to be rewritten and the parameters for rewriting are obtained: (a) Self-boot and (b) Host boot (a) Self-boot Self-booting transfers program code data from the data memory to the instruction memory. Boot parameters are set in the data memory (Y memory: from address 0x4000) in the case of reset boot, and in the registers in the case of reboot. To configure a stand-alone system with the PD77016 , store boot parameters and program data in an external ROM, and execute reset boot in the self-boot mode. To configure a stand-alone system with a ROM version product (PD77015, 77017, 77018, 77018A, or 77019), store boot parameters and program data in the ROM area, and execute
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reset boot in the self-boot mode. The boot parameters are always stored in the internal Y ROM, whereas the program data can be stored either in the internal or external X or Y ROM. The PD77019-013 cannot execute self-boot from the internal data ROM because its internal data ROM is masked. However, because the boot parameters for self-boot are set in advance, self-boot can be executed only from the external Y data memory. Figure 4-1 shows a configuration example of a system in the self-boot mode.
Figure 4-1. Example of Self-boot System Configuration (a) PD77016
Instruction memory (SRAM, etc.) (Option as necessary) WE 16 32 VDD IA0-IA15 ID0-ID31 A/D D/A SI SO PWR P0 P1 RESET
PD77016
RESET
DA0-DA15 16 A0-A15
D0-D15 (7) MRD 16 (8) D0-D15 (7) OE
Data memory (ROM, etc.) (for boot, data)
(b) PD77015, 77017, 77018, 77018A, 77019
VDD A/D D/A SI ROM SO P0 P1 RESET MRD
PD77015/ 17/18/18A/19
D0-D15 (7) 16 (8) D0-D15 (7) Data memory (ROM, etc.)
RESET
DA0-DA13 14 A0-A13
OE
Note
Note Use this as an option as necessary. This memory is essential for the PD77019-013.
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(b) Host boot When host boot is executed, the PD7701x reads program code data through the host interface and transfers this data to the instruction memory. In the case of reset boot, the boot parameters are read through the host interface prior to the program code data read. In the case of reboot the boot parameters have to be set to some registers by the application program. Host boot can be used in a system where a CPU is connected to the host interface and a program is downloaded from that CPU to the PD7701x. Figure 4-2 shows an example of host boot system configuration.
Figure 4-2. Configuration Example of Host Boot System (a) PD77016
Instruction memory (SRAM, etc.) (Option as necessary)
WE
16
IA0-IA15
32
ID0-ID31 PWR P0
VDD
P1 RESET INT Boot RQ WR RD Address Data WR RD Address Data
PD77016
CPU
Data memory
HD0-HD7 HA0,HA1
HCS
HWR
HRD
8
2
Data bus Address bus Control bus
(b) PD77015, 77017, 77018, 77018A, 77019
VDD
PD77015/ 77017/77018/ 77018A/77019
HD0-HD7 HA0,HA1 HCS HWR
P0 P1 RESET INT HRD Boot RQ WR RD Address Data WR RD Address Data
CPU
Data memory
8
2
Data bus Address bus Control bus
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4.2 Boot Modes
(3) Classification by transfer word size
This classification is meaningful for self-boot only. The parameter for self-boot can specify the size for data memory reading as follows:
* 16-bit word/1 address (word boot): Refer to Figure 4-3. * 8-bit byte/1 address (byte boot): Refer to Figure 4-4.
In the case of word boot, therefore, two data memory addresses correspond to one instruction step; in the case of byte boot, four data memory addresses correspond to one instruction step. Normally, for self-boot at reset, the boot parameters and program code data are fixed in ROM. With the PD77016, if the ROM in which the parameters and program code data are stored is configured of 8 bits (1 byte)/1 address, a cost reduction can be achieved when a small-scale system is organized.
Figure 4-3. Illustration of Word Boot
Data memory 15 Low address 31 0 0 31 Instruction memory 0
High address
Figure 4-4. Illustration of Byte Boot
Data memory 7 Low address 0 31 Instruction memory 0
31
0
High address
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4.3 Boot at Reset
4.3
Boot at Reset
The PD7701x family executes the boot program located at address 0 after hardware reset is input. The boot program first reads general-purpose port pins P0 and P1 and determines the boot mode (self-boot or host boot) depending on the bit pattern. Table 4-1 shows the relation between the bit pattern of P0 and P1 at reset and the boot mode.
Table 4-1. P0 and P1 Reset Values and Boot Modes
P1 0 0 1 1 P0 0 1 1 0 Reaction (boot mode) Does not execute boot. Branches to address 0x200.Note Executes host boot, and then branches to address 0x200. Executes self-boot, and then branches to address 0x200. Setting prohibited
Note This setting is used by the DSP when it must be reset, to execute reset boot once on power ON and subsequently to return from a power-down mode.
When reset boot is executed, no parameter to specify the load starting address of the instruction memory is provided. The instruction memory will always be loaded from the fixed address 0x200 (starting address of internal RAM area)
Caution
With the PD77016, only the internal instruction memory is subject to reset boot. Use reboot for booting up the external instruction memory.
4.3.1 Self-boot operation
(1) Parameters for self-booting
The following parameters are first read from address 0x4000 of the Y memory: * Memory space command * Word boot or byte boot command Table 4-2 shows the contents of the parameters.
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Table 4-2. Parameters for Self-booting (0x4000: Y)
Bit no. 0 Value 0 1 1 0 Meaning Y memory boot. Reads program codes from Y memory space. X memory boot. Reads program codes from X memory space. Note Word boot. Reads data memory in 16-bit units. Therefore, one instruction memory address corresponds to two addresses of data memory. Refer to Figure 4-3. Byte boot. Reads data memory in 8-bit units. Therefore, one instruction memory address corresponds to four data memory addresses. Refer to Figure 4-4. In byte boot mode In word boot mode
1
2-7 2-15
Note
Any Any
All boot parameters are read from the Y memory space even when X memory boot is specified. At this time, seven wait cycles are set as the data memory wait cycles. The parameter addresses are as follows: * 0x4000: Y-0x4004: Y (in word boot mode) * 0x4000: Y-0x4009: Y (in byte boot mode)
Caution
The registers DWTR, IWTR, R7, DP3 and DP7 are changed by the boot routine.
(a) Parameters for word boot Table 4-3 shows the memory map of the parameters for word boot.
Table 4-3. Memory Map of Parameters for Word Boot
Address 0x4000: Y 0x4001: Y 0x4002: Y 0x4003: Y 0x4004: Y Memory value 16/8 bits, X/Y Value set to DWTR Value set to IWTR Starting address of data memory that stores program to be read Number of steps of programNote
Note This value is calculated with 32 bits = 1 word, and does not indicate the number of words when the program is located in the external data memory.
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(b) Parameters for byte boot Table 4-4 shows the memory map of the parameters for byte boot.
Table 4-4. Memory Map of Parameters for Byte Boot
Address 0x4000: Y 0x4001: Y 0x4002: Y 0x4003: Y 0x4004: Y 0x4005: Y 0x4006: Y 0x4007: Y 0x4008: Y 0x4009: Y Memory value 16/8 bits, X/Y -- Value set to DWTR (lower byte) Value set to DWTR (higher byte) Value set to IWTR (lower byte) Value set to IWTR (reserved) Starting address of data memory storing program to be read (lower byte) Starting address of data memory storing program to be read (higher byte) Number of steps of programNote (lower byte) Number of steps of programNote (higher byte)
Note This value is calculated with 32 bits = 1 word, and does not indicate the number of words when the program is located in the external data memory.
(2) Parameters for self-boot of PD77019-013
With the PD77019-013, the following information is defined in advance as boot parameters.
0x4000: Y 0x4001: Y 0x4002: Y 0x4003: Y 0x4004: Y
0 (Y memory boot/word boot) 0xC0C0 (set value of DWTR: 7 wait) 0 (set value of IWTR: 0 wait) 0xC000 (first address of boot code storage destination) 0x1000 (number of steps of program: 4K words)
To execute self-boot, connect 8K words or more of 16-bit PROM (that can be accessed with 7 wait cycles) from address 0xC000 of the external Y data area, and store the codes for boot in that PROM.
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4.3 Boot at Reset
4.3.2 Host boot operation
When the host boot mode is executed, boot parameters and op codes are obtained through the host interface. Figure 4-5 shows a conceptual drawing of the host boot procedure.
Figure 4-5. Host Boot Procedure
Host CPU
PD7701x
Wait function is used for handshaking between host interface and PD7701x. Reads and sets value to IWTR.
[Polling] Value to be set to IWTR is output. (lower byte, higher byte)
[Polling] Number of booted instructions is output. (lower byte, higher byte)
Reads number of program steps.
[Polling] Specifies handshaking between host CPU and host interface.
Sets handshake mode to HST.
[Polling] Outputs op code (little endian)
Executes boot.
(1) Setting of host interface
Prior to host boot operations, initial settings for the host interface are performed as follows. However, these settings, except the settings of HAWE bit and transfer size, are overwritten by the HST setting parameters to be sent later. HST=0x0401 * HAWE = 1 : Uses wait function. * HREM = 0 : Does not mask HRE. * HWEM = 0 : Does not mask HWE. * Transfer size = 16-bit mode : Host writes the specified parameters to HDT starting with the lower 8 bits and then the higher 8 bits (this is not the set value of HST but a host boot rule).
Caution
The value of the HST register is changed when the HST setting parameters are set in the boot process.
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Boot Function 4.3 Boot at Reset
(2) Parameters for host boot
If reset boot is executed, the following parameters are used for host boot: * IWTR set value : Determines the number of wait cycles of the instruction memory. For the meaning of the set value, refer to the paragraph (f) "Wait function of external instruction memory" in section 3.4.2 (1).
* Number of booted instructions : Indicates the number of instruction steps of the program to be booted (number of instructions to be booted). The number of data actually transferred is two times the number of instruction steps. * HST setting value : Data to be set to HST. All the bits of HST, except HAWE (bit 10), are set. HAWE is set to "1", regardless of the value set to HST. : The lower 16 bits (bits 15-0) and the higher 16 bits (bits 31-16) of a 32-bit op code are transferred in this order. If the host interface is set to 8-bit width, therefore, bits 7-0, 15-8, 23-16, and 31-24 are transferred in that order.
* Instruction code
Caution
When the PD77015, 77017, 77018, 77018A, or 77019 is used, dummy data for IWTR set values must be transferred though IWTR set values are not specified.
The above parameters are transferred from the host in the following sequence: 1st transfer 2nd transfer polling 3rd transfer 4th transfer polling 5th transfer 6th transfer polling 7th transfer 8th transfer polling 9th transfer 10th transfer polling 11th transfer
* *
: Lower 8 bits of IWTR set valueNote 1 : Higher 8 bits of IWTR set valueNote 1 : Wait for PD7701x loaded data from HDT (in) : Lower 8 bits of number of booted instructions : Higher 8 bits of number of booted instructions : Wait for PD7701x loaded data from HDT (in) : Lower 8 bits of HST set value : Higher 8 bits of HST set value : Wait for PD7701x loaded data from HDT (in) : 1st op code (bits 7-0) : 1st op code (bits 15-8) : Wait for PD7701x loaded data from HDT (in) : 1st op code (bits 23-16) : 1st op code (bits 31-24) : Wait for PD7701x loaded data from HDT (in) : 2nd op code (bits 7-0)
* *
(4n+6)th transfer polling
: nth op code (bits 31-24)Note 2 : Wait for PD7701x loaded data from HDT (in)
Notes 1. Dummy data are transferred when the PD77015, 77017, 77018, 77018A, or 77019 is used. 2. The total number of transferred bytes is 4n + 6, where the number of transferred op codes is n.
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4.4 Boot Subroutine (reboot)
4.4
Boot Subroutine (reboot)
Booting by using the boot subroutine to rewrite program data in the instruction memory is called reboot. Usually, the instruction memory cannot be rewritten from an application program. However, by using the reboot function (or by calling a boot subroutine), new instructions can be written to the instruction memory. Some boot subroutines are provided in the boot ROM and their entry points are made public to users as shown in Table 4-5. To execute reboot, set specified parameters to registers, then execute the CALL instruction jumping to a reboot entry address. The registers and pins not related to reboot retain the status when the boot subroutine is called during and after reboot, and are not initialized by reboot.
Table 4-5. Boot Subroutine Entry Points
Reboot mode Self-boot X memory Word reboot Byte reboot Y memory Word reboot Byte reboot Host boot Host reboot Entry point address 0x2 0x4 0x1 0x3 0x5
Cautions 1. Bear in mind the following points when executing reboot:
* The register values are not preserved. * One level of the program stack is used (at entry). * One level of the loop stack is used. * Disable all interrupts throughout the reboot period. (If an interrupt is acknowledged during reboot, normal operation cannot be guaranteed). * After reboot completion, execution returns to the instruction next to the CALL instruction which called the reboot subroutine.
2. The registers DWTR, IWTR, R7, DP3, DP7, HST and HDT are changed by the boot routine.
4.4.1 Parameters of X memory word or byte reboot
The reboot type that locates op codes in the X memory is called X reboot. X reboot can be classified into two modes: X memory word reboot that locates a 16-bit word per one data memory address, and X memory byte reboot that locates an 8-bit byte per one data memory address. In both modes, the following parameters are set to specified registers, and the entry points shown in Table 4-5 are called.
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4.4 Boot Subroutine (reboot)
* R7L : Number of instruction steps to be rebooted * DP3: Starting address of X memory storing op code * DP7: Starting address of instruction memory to be loaded
Cautions 1. The values in the parameter registers are not preserved. 2. Set IWTR and DWTR as necessary.
4.4.2 Parameters of Y memory word or byte reboot
The reboot type that locates op codes in the Y memory is called Y reboot. Y reboot can be classified into two modes: Y memory word reboot that locates a 16-bit word per one data memory address, and Y memory byte reboot that locates an 8-bit byte per one data memory address. In both modes, the following parameters are set to specified registers, and the entry points shown in Table 4-5 are called. * R7L : Number of instruction steps to be rebooted * DP3: Starting address of instruction memory to be loaded * DP7: Starting address of Y memory storing op code
Cautions 1. The values in the parameter registers are not preserved. 2. Set IWTR and DWTR as necessary.
4.4.3 Parameters for host reboot
To reboot from the host interface, the following parameters are set to specified registers, and the entry points shown in Table 4-5 are called. * R7L : Number of instruction steps to be rebooted * DP3: Starting address of instruction memory to be loaded
Cautions 1. The values in the parameter registers are not preserved. 2. Set HST and IWTR as necessary. However, be sure to set HAWE of HST to "1" (to use wait) before reading the reboot routine. 3. HDT must be empty (no data should remain before read) when reboot is started.
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Chapter 4 Boot Function
4.5 Boot Time
4.5
Boot Time
Table 4-6 shows the time required for booting.
Table 4-6. Boot Time
Boot mode Boot Self-boot Self-boot & Word boot & Byte boot Boot time (unit : number of cycles) Min. Max. Min. Max. 49 + 3D + (4 + 2D + I) x W 51 + 3D + (4 + 2D + I) x W 70 + 6D + (10 + 4D + I) x W 72 + 6D + (10 + 4D + I) x W
Host boot Reboot Self-reboot & Word boot Self-reboot & Byte boot Reboot
Remarks W : number of instruction words booted D : data memory wait cycles I : instruction memory wait cycles
29 + 4D + (4 + I) x W or longer (depending on access speed of host CPU) 6 + (4 + 2D + I) x W 6 + (10 + 4D + I) x W 6 + (4 + I) x W or longer (depending on access speed of host CPU)
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Chapter 5
Development Tools
This chapter introduces the development tools for the PD7701x family.
1 2 3 4 5 6 A B C
Caution
This chapter only introduces currently available development tools. For details, refer to the manual of each tool.
5.1
Software Tools
The following type of software tool is available: * WindowsTM-based development environments
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Chapter 5 Development Tools
5.1 Software Tools
5.1.1 Integrated development environment work bench (WB77016)
WB77016 is a development environment that unifies Relocatable Assembler, Linker, Editor, and Make Utility. It allows an efficient flow of operations, from program editing to the creation of object programs and software simulation startup.
5.1.2 Software simulator (SM77016, SM77016-H)
SM77016 and SM77016-H simulate the operation of the PD7701x Family. The focus of the simulation are the program control unit, external memory, instruction memory, host interface, serial interface, and the I/O ports. The SM77016-H can execute simulation at high speeds by coding the program as a 32 bit Windows95 compatible program.
5.1.3 C compiler (InterToolsTM 77016)
This product was developed by TASKING, Inc., a US company. PD7701x Family software applications can be created through a high-performance C cross-compiler that compiles with the ANSI standards. When debugging, use the software simulator.
5.1.4 System software for in-circuit emulator (ID77016)
The objective of this software package is the control of the IE-77016-PC. The IE-77016 can be manipulated through a user interface that is the same as the software simulator interface.
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5.2 Hardware Tools
5.2
Hardware Tools
5.2.1 In-circuit emulator
(1) In-circuit emulator : IE-77016-PC
Host machine IBM PC/ATTM
Code IE-77016-PC
Remark When using the IE-77016-PC, system software is necessary in addition to the above basic system. Refer to 5.1.4 "system software for in-circuit emulator (ID77016)".
5.2.2 Options for in-circuit emulators
The following options are available for the IE-77016-PC. Use them as necessary.
Code Emulation board for in-circuit emulator IE-77016-CM-EM6 EB-77017
Corresponding host machine IBM PC/AT
PD77017 evaluation board
Adapter for EB-77017 board
TGC-100SDW (Tokyo Eletech Corp.)Note
Note Consult NEC when you purchase this product.
(1) Emulation board for in-circuit emulator
This emulation board which is mounted in the IE-77016-PC, emulates PD7701x operations. This board is provided with external instruction memory (32K words x 32 bits) and external X and Y data memories (16K words x 16 bits each) in addition to one PD77016.
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Chapter 5 Development Tools
5.2 Hardware Tools
(2) PD77017 evaluation board
This evaluation board is used to emulate the PD77015/77017 by using the PD77016. One side of this board is connected to the IE-77016-PC interface cable, and the other side is equipped with the adapter to be connected to the target system board (EB-77017). This board also serves as a level converter between the IE-77016-PC interface cable (5-V interface) and the PD77015/77017 debugging pins (3-V interface) on the target system where the PD77015/77017 has been mounted. This board is provided with an external instruction memory (32K words x 32 bits), external X and Y data memories (32K words x 16 bits each), and a level conversion circuit (from 5 V to 3 V), in addition to one PD77016. To emulate the PD77018, 77018A, and 77019, consult NEC.
(3) Adapter for EB-77017 board
This adapter is mounted on the EB-77017 of the evaluation board to connect the target system of the PD77015/77017. It is provided with 0.5-mm pitch, 100-pin TQFP package pins equivalent to the PD77015/ 77017 pins (for target system connection) and a connector (for EB-77017 connection).
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Appendix A
Device Summary
This appendix summarizes the functions of the PD7701x family described in this manual. Use this appendix when developing your system after having gained a general understanding of the features of this device.
1 2 3
A.1 Register List
A.1.1 CPU registers
(1) Stack (STK)
Bit 15 Bit 0 x 15 levels
4 5
Program counter push/pop
Refer to section 3.4.2 "Program execution control block".
(2) Stack pointer (SP)
Bit 15 0 0 0 0 0 0 0 0 0 0 0 0 Stack address Bit 0
6 A
External interrupt master si1 4 int4 3 int3 2 int2 1 int1 0
Refer to section 3.4.2 "Program execution control block".
(3) Status register (SR)
Interrupt enable flag EI 15 EP 14 EB 13 LF ho 12 11 10 9 hi 8 so2 7 si2 6 so1 5 Reserved Interrupt enable flag for each cause On-chip I/O device
B C
interrupt enable flag = 1: interrupt disabled interrupt enable flag = 0: interrupt enabled Refer to section 3.4.4 "Interrupt".
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A.1 Register List
(4) Interrupt enable flag stack register (EIR)
Bit 15 EI EP EB E3 E4 E5 E6 E7 E8 Bit 0 E9 E10 E11 E12 E13 E14 E15
Refer to section 3.4.4 "Interrupt".
(5) Loop start address register (LSA)
Bit 15 Bit 0
Loop start address
Refer to section 3.4.3 "Flow control block".
(6) Loop end address register (LEA)
Bit 15 Bit 0
Loop end address
Refer to section 3.4.3 "Flow control block".
(7) Loop counter (LC)
Bit 15 LF Count value setting field (setting range: 1 to 0 x 7FFF) Bit 0
LF=0: loop in progress LF=1: end of loop (not in progress) Refer to section 3.4.3 "Flow control block".
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A.1 Register List
(8) Loop stack (LSTK)
Bit 15 LSR1 Loop start address push/pop Bit 0
Bit 15 LSR2 Loop end address push/pop
Bit 0 x 4 levels
Bit 15 LSR3 LF Loop counter push/pop
Bit 0
Refer to section 3.4.3 "Flow control block".
(9) Loop stack pointer (LSP)
Bit 15 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0
Loop STK address
Refer to section 3.4.3 "Flow control block".
(10) Repeat counter (RC)
Bit 15 RF Count value setting field (setting range: 1 to 0 x 7FFF) Bit 0
RF=0: Repeat in progress RF=1: End of repeat (not in progress) Refer to section 3.4.3 "Flow control block".
(11) General-purpose registers (R0 to R7)
Bit 39 32 31 16 15 Bit 0
R0E-R7E
R0H-R7H R0EH-R7EH R0-R7
R0L-R7L
Refer to section 3.6 "Operation Unit".
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A.1 Register List
(12) Data pointers (DP0-DP7)
Bit 15 Bit 0
DP0-DP7
DP0-DP3: Address of X-memory space DP4-DP7: Address of Y-memory space Refer to section 3.6 "Operation Unit".
(13) Index registers (DN0-DN7)
Bit 15 Bit 0
DN0-DN7
DN0-DN7: Modify DP0-DP7 Refer to section 3.5 "Data Addressing Unit".
(14) Modulo registers (DMX, DMY)
Bit 15 Bit 0
DMX, DMY
DMX: The ring count range for DP0-DP3 is specified DMY: The ring count range for DP4-DP7 is specified Refer to section 3.5 "Data Addressing Unit".
(15) Error status register (ESR)
Bit 15 Bit 0 ovf ste lse bac
ovf: ste: lse: bac:
Overflow error flag Stack error flag Loop stack error flag Bus access error flag 0: No error 1: Error
Refer to section 3.4.5 "Error status register".
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A.1 Register List
A.1.2 Peripheral registers
(1) Peripheral register map
X/Y memory address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 0x3809 0x380A-0x383F
Register name SDT1 SST1 SDT2 SST2 PDT PCD HDT HST DWTR IWTR Reserved
Function Serial data register 1 Serial status register 1 Serial data register 2 Serial status register 2 Port data register Port command register Host data register Host status register Data memory wait cycle register Instruction memory wait cycle register
Peripheral name Serial IO Serial IO Serial IO Serial IO IO Port IO Port Host IO Host IO Wait Reg Wait Reg --
Load/Store (L/S) L/S L/S L/S L/S L/S L/S L/S L/S L/S L/S --
Do not access this area.
(2) Serial data registers (SDT1: 0x3800:X/:Y, SDT2: 0x3802:X/:Y)
Bit 15 87 Bit 0
8-bit I/O 16-bit I/O
MSB
LSB
Refer to section 3.7.3 "Serial interface".
(3) Serial status registers (SST1: 0x3801:X/:Y, SST2: 0x3803:X/:Y)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO SI SO SI SS SL SI SI TF TF BL BL WE WE CM EF
Reserved
SS SL SS SL ER ER EF EF
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A.1 Register List
Bit 15
Name SOTF
Load/store Bit function L/S L/S Serial output transfer format setting bit * 0: Serial output with MSB first * 1: Serial output with LSB first Serial input transfer format setting bit * 0: Serial input with MSB first * 1: Serial input with LSB first Serial output word length setting bit * 0: 16-bit serial output * 1: 8-bit serial output Serial input word length setting bit * 0: 16-bit serial input * 1: 8-bit serial input SDT store wait enable bit * 0: Does not use store wait function. * 1: Uses store wait function. Inserts wait cycles when PD7701x stores to SDT (out) with SSEF=0. SDT load wait enable bit * 0: Does not use load wait function. * 1: Uses load wait function. Inserts wait cycles when PD7701x loads from SDT(in) with SLEF=0. Serial input continuous mode setting flag * 0: Enters single serial input mode after completion of current serial input. * 1: Enters continuous serial input mode to start serial input. Single serial input enable flag * 1: Starts serial input processing in single serial input mode (only once). The SIEF flag that is set to 1 is automatically reset in the next instruction cycle. Reserved bits * Value cannot be set to these bits. * Undefined when read. SDT store error flag * 0: No error * 1: Error (Set to 1 when PD7701x stores data to SDT(out) with SSEF=0.) * Once set, this flag does not change its status until 0 is written by PD7701x. SDT load error flag * 0: No error * 1: Error (Set to 1 when PD7701x loads data from SDT(in) with SLEF=0.) * Once set, this flag does not change its status until 0 is written by PD7701x. SDT store enable flag * Set to 1 when contents of SDT(out) is transferred to serial output shift register. * Cleared to 0 when PD7701x stores data to SDT(out). SDT load enable flag * Set to 1 when contents the shift register for serial input is transferred to STD (in). * Cleared to 0 when PD7701x loads data from SDT(in).
14
SITF
L/S
13
SOBL
L/S
12
SIBL
L/S
11
SSWE
L/S
10
SLWE
L/S
9
SICMNote
L/S
8
SIEFNote
L/S
7-4
Reserved
--
3
SSER
L/S
2
SLER
L/S
1
SSEF
L
0
SLEF
L
Note
Following table shows an example of combination of SICM and SIEF. When continuous data such as speech data is input, use status 2 (SICM=1, SIEF=0).
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A.1 Register List
Remarks 1.
Combination of SICM and SIEF Bits
Example of combination 1 2 3 4
2.
Bit 9 SICM 0 1 0 1
Bit 8 SIEF 0 0 1 1
Function * Status transition mode. * Continuous serial input mode. * Single serial input mode. * The setting of this combination is prohibited.
Setting of SST after hardware reset: 0x0002.
Refer to section 3.7.3 "Serial interface".
(4) Host data register (HDT: 0x3806:X/:Y)
Bit 15 87 Bit 0
8-bit I/O 16-bit I/O
MSB
LSB
Refer to section 3.7.4 "Host interface".
(5) Host status register (HST: 0x3807:X/:Y)
Bit 15 14 13 12 Reserved 11 10 9 8 7 6 5 4 3 2 1 0 HA HR HW HR HW HS HL HR HW WE EM EM UF1 UF0 ER ER ER ER EF EF
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A.1 Register List
Bit 15-11
Name Reserved
R/W from host --
Load/store (L/S) from PD7701x --
Bit function Reserved bits * No value can be set to these bits. * These bits are undefined when read. HDT access wait enable bit * 0: Wait is not used * 1: Wait is used Wait cycles are inserted if the PD7701x attempts to store data to HDT(out) while HREF=1, or to load data from HDT(in) while HWEF=1. HRE mask bit * 0: Does not mask. HRE changes according to the HREF status (refer to below). * 1: Masks. HRE becomes inactive (high level). HWE mask bit * 0: Does not mask. HWE changes according to the HWEF status (refer to below). * 1: Masks HWE becomes inactive (high level). User's flag User's flag Host read error flag * 0: No error * 1: Error Set to 1 when host CPU reads HDT when HREF is 0. * Once set to 1, it does not change until 0 is written by program. Host write error flag * 0: No error * 1: Error Set to 1 when host CPU writes HDT when HWEF is 0. * Once set to 1, it does not change until 0 is written by program. HDT store error flag * 0: No error * 1: Error Set to 1 when PD7701x stores to HDT when HREF is 1. * Once set to 1, it does not change until 0 is written by program. HDT load error flag * 0: No error * 1: Error Set to 1 when PD7701x loads from HDT when HWEF is 1. * Once set to 1, it does not change until 0 is written by program. Host read enable flag * 0: Read disabled * 1: Read enabled Set to 1 when the PD7701x stores data to HDT. Cleared to 0 when host CPU reads higher byte of HDT. * Ignored when written. Host write enable flag * 0: Write disabled * 1: Write enabled Set to 1 when the PD7701x loads data from HDT. Cleared to 0 when host CPU writes higher byte of HDT. * Ignored when written.
10
HAWE
R
L/S
9
HREM
R
L/S
8
HWEM
R
L/S
7 6 5
UF1 UF0 HRER
R R R
L/S L/S L/S
4
HWER
R
L/S
3
HSER
R
L/S
2
HLER
R
L/S
1
HREF
R
L
0
HWEF
R
L
Remark
The HST setting after hardware reset: 0x0301 * No wait function * HRE/HWE mask: masked * Host write enabled * Host read disabled
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A.1 Register List
Host I/O error flag setting condition
Error flag name HRER HWER HSER HLER Cause Host read when HREF = 0 Host write when HWEF = 0 Store to HDT when HREF = 1 Load from HDT when HWEF = 1 Releasing condition Reset by hardware reset or program
(6) Port data register (PDT: 0x3804:X/:Y)
Bit 15 P3 P2 Bit 0 P1 P0
0: Low level 1: High level Refer to section 3.7.5 "General-purpose input/output port".
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A.1 Register List
(7) Port command register (PCD:0x3805:X/:Y)
Bit 15 Name BE Category Load/store Bit function (L/S) Bit manipulation enable bit * 0: Does not manipulate bit. * 1: Manipulates bit Manipulation method is specified by B1, B0, and PSR. * Undefined when read. Port set/reset specification bit * 0: Reset (low level) * 1: Set (high level) * Manipulation port is specified by B1 and B0. * Valid when BE = 1. * Undefined when read. Mode setting enable bit * 0: Does not set mode. * 1: Sets mode. Contents to be set are specified by IO and M3-M0. * Undefined when read. Input/output specification bit * 0: Specifies input mode. * 1: Specifies output mode. * Port to be set is specified by M3-M0. * Valid when ME = 1. * Undefined when read. Reserved bits * No value can be set to these bits. * Undefined when read. Bit manipulation port specification bits * B1, B0 = 00: P0 01: P1 10: P2 11: P3 * Set/reset is specified by PSR. * Valid when BE = 1. * Undefined when read. Reserved bits * No value can be set to these bits. * Undefined when read. Mode setting port specification bits M3 = 0: P3 unselected, 1: P3 selected M2 = 0: P2 unselected, 1: P2 selected M1 = 0: P1 unselected, 1: P1 selected M0 = 0: P0 unselected, 1: P0 selected * Selection can be specified independently. Input/output mode status bits M3 = 0: P3 input mode, 1: P3 output mode M2 = 0: P2 input mode, 1: P2 output mode M1 = 0: P1 input mode, 1: P1 output mode M0 = 0: P0 input mode, 1: P0 output mode
Bit manipulation S
14
PSR
Bit manipulation S
13
ME
Mode setting
S
12
IO
Mode setting
S
11, 10
Reserved --
--
9, 8
B1, B0
Bit manipulation S
7-4
Reserved --
--
3-0
M3-M0
Mode setting
S
Mode status
L
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A.1 Register List
(8) Data Wait Cycle Register (DWTR )
(a) PD77016
X data memory 0xFFFF D field 16K words 0xC000 0xBFFF C field 16K words 0x8000 0x7FFF B field 16K words 0x4000 0x3FFF 0x0000 15 14 DWTR H field 13 12 11 10 9 8 7 0x4000 0x3FFF 0x0000 6 5 4 3 2 1 0 0x8000 0x7FFF F field 16K words 0xC000 0xBFFF G field 16K words 0xFFFF H field 16K words Y data memory
G field
F field
D field
C field
B field
(b) PD77015, 77017, 77018, 77018A, 77019
X data memory 0xFFFF D field 16K words 0xC000 0xBFFF 0x8000 0x7FFF 0x4000 0x3FFF 0x0000 15 14 DWTR H field 13 12 11 10 9 8 7 0xC000 0xBFFF 0x8000 0x7FFF 0x4000 0x3FFF 0x0000 6 5 4 3 2 1 0 0xFFFF H field 16K words Y data memory
D field
Caution
* With the PD77016, writing data to bits 9, 8, 1, and 0 is ignored. These bits are undefined when read. * With the PD77015, 77017, 77018, 77018A, and 77019 writing data to bits 13-8 and 5-0 is ignored. These bits are undefined when read.
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A.1 Register List
(c) Set Value of Field (Number of Wait Cycles)
Bit 0 0
Wait cycles 0
Remark 1-cycle access: SRAM etc. with an access time of about 8 ns is connected (at 33 MHz).
0
1
1
2-cycle access: SRAM etc. with an access time of about 35 ns is connected (at 33 MHz).
1
0
3
4-cycle access: SRAM etc. with an access time of about 85 ns is connected (at 33 MHz).
1
1
7
8-cycle access: Mask ROM etc. with an access time of about 150 ns is connected (at 33 MHz)
Caution
When DWTR is set, the specified number of wait cycles becomes valid when an instruction immediately after the instruction that has set the data to DWTR.
Refer to section 3.5.2 "Data memory space".
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A.1 Register List
(9) Instruction Wait Cycle Register (IWTR )
Instruction memory
0xFFFF ID field 16K words 0xC000 0xBFFF IC field 16K words 0x8000 0x7FFF IB field 16K words 0x4000 0x3FFF 0x0000 Internal instruction memory area 16K words
15 14 IWTR
13
12 11 --
10
9
8
7
6
5
4
3
2
1 --
0
ID field IC field IB field
Bits 0 0 0 1
No. of wait cycles 0 1
Remarks 1 cycle access: Connects SRAM with access time of 8 ns (at 33 MHz) 2 cycle access: Connects SRAM with access time of 35 ns (at 33 MHz)
1
0
3
4 cycle access: Connects SRAM with access time of 85 ns (at 33 MHz)
1
1
7
8 cycle access: Connects mask ROM with access time of 150 ns (at 33 MHz)
Cautions 1. Data written to bits 15 through 8, 1, and 0 are ignored. The contents of bits 15 through 8, 1, and 0 are undefined when they are read. 2. With the PD77015, 77017, 77018, 77018A, and 77019, data written to IWTR is ignored, and undefined data is read from IWTR.
Refer to section 3.4.2 "Program execution control block".
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Appendix A Device Summary
A.2 Interrupt Vector Table
A.2 Interrupt Vector Table
Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C Internal/external Internal -- -- -- External External External External Internal Internal Internal internal Internal Internal -- -- Interrupt cause Reset Reserved Reserved Reserved INT1 INT2 INT3 INT4 SI1 input SO1 output SI2 input SO2 output HI input HO output Reserved Reserved
A.3 CPU Registers to Be Initialized and Initial Values
Register name SR Initial value 0xF000 Remark All the interrupts of the respective causes are enabled, and the interrupts are disabled at both the current and past levels. Also indicates that a loop instruction is not under execution. Address 0 is a boot area and execution branches to address 0x200 after boot processing. Therefore, the reset entry as the user area is at address 0x200. - Indicates that a loop instruction is not under execution. The count value itself is undefined. - Indicates that a repeat instruction is not under execution. The count value itself is undefined. Indicates the interrupts are disabled at both the current and past levels. -
PC
0
SP LC LSP RC EIR ESR
0 0b1xxx xxxx xxxx xxxx 0 0b1xxx xxxx xxxx xxxx 0xFFFF 0
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A.4 Memory-Mapped Registers to Be Initialized and Initial Values
A . 4 Memory-Mapped Registers to Be Initialized and Initial Values
Register name SST1, SST2 Initial value 0x0002 Remark Serial interface is initialized as follows: * MSB first for both input and output * 16 bits long for both input and output * Does not use wait function for loading/storing SDT * Status transition mode * Clears error flag of SDT loading/storing * Enables data storing to SDT * No data is loaded from SDT I/O port is initialized as follows: * Bits are not manipulated * Mode is not set Host interface is initialized as follows: * Does not use wait function for HDT access * Disables both HRE and HWE functions * Clears both UF0 and UF1 to zero * Clears error flag for host read/write * Clears error flag for HDT load/store * Disables reading from host * Enables writing from host
PCD
0x0000
HST
0x0301
A.5 Pins to Be Initialized and Initial Status
Pin name X/Y DA0-DA15 D0-D15 IA0-IA15Note 2 ID0-ID31Note 2 PWRNote 2 MRD, MWR, BSTB SORQ1, SORQ2, SIAK1, SIAK2 SO1, SO2 HRE, HWE P0-P3 TICE High-level outputNote 1 Initial value
Low-level outputNote 1 High impedance Low-level output (high impedance during reset) High impedance High-level output (high impedance during reset) High-level outputNote 1 Low-level output High impedance High-level output Input status Low-level output
Notes 1. These pins go into a high-impedance state when the bus is released (HOLDAK = 0). The bus is released even during reset by clearing HOLDRQ to 0. 2. PD77016 only
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A.6 Status of Output Pins during Reset to Release STOP Mode
A.6 Status of Output Pins during Reset to Release STOP Mode
Pin name CLKOUT X/Y DA0-DA13 D0-D15 MRD MWR BSTB HOLDAK HD0-HD7 HRE HWE SO1, SO2 SIAK1 SORQ1 P0-P3 Input status High impedance Low level High impedance High level Initialized status System clock Note Low level 0x0000 High impedance High level Status during reset to release STOP mode UndefinedNote Undefined
Note If CLKOUT is fixed to low level by mask option, CLKOUT is low in the initialized status and the status during reset to release the STOP mode.
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A.7 Memory Map
A.7 Memory Map
A.7.1 Instruction memory map
PD77016
0xFFFF System (24K words) System (36K words) 0xA000 0x9FFF Internal instruction ROM (24K words) Internal instruction ROM (24K words) System (24K words)
PD77015
PD77017
PD77018, 77018A
PD77019Note
External instruction memory (48K words) 0x5000 0x4FFF 0x4000 0x3FFF System (14K words) 0x0800 0x07FF Internal instruction RAM (1.5K words) 0x0240 0x023F 0x0200 Vector area (64 words) 0x01FF System (256 words) 0x0100 0x00FF 0x0000 Boot-up ROM (256 words) 0x0300 0x02FF
System (44K words)
0x7000 0x6FFF Internal instruction ROM (4K words) System (15.25K words)
Internal instruction RAM (256 words)
Internal instruction ROM (12K words) System (15.25K words)
Internal instruction RAM (256 words)
System (15.25K words)
Internal instruction RAM (256 words)
0x1200 System (11.5K words) 0x11FF Internal instruction RAM (4K words) Vector area (64 words) System (256 words)
Vector area (64 words) System (256 words)
Vector area (64 words) System (256 words)
Vector area (64 words) System (256 words)
Boot-up ROM (256 words)
Boot-up ROM (256 words)
Boot-up ROM (256 words)
Boot-up ROM (256 words)
Caution No program or data must be stored to the addresses reserved for the system, nor must these addresses be accessed. If any of these addresses is accessed, normal operation of the PD7701x family is not guaranteed. Note The PD77019-013 does not have the internal ROM of the PD77019.
A.7.2 Data memory map (X/Y)
PD77016
0xFFFF
PD77015
External data memory (16K words)
PD77017
External data memory (16K words)
PD77018, 77018A, 77019Note
External data memory (16K words) System (20K words)
0x7000 0x6FFF
0xC000 0xBFFF
External data memory (48K words)
0x4800 0x47FF 0x4000 0x3FFF 0x3840 0x383F 0x3800 0x37FF
System (30K words)
0x5000 0x4FFF
System (28K words)
Data ROM (2K words)
System (1984 words) Peripheral (64 words)
Data ROM (4K words)
System (1984 words) Peripheral (64 words)
Data ROM (12K words)
System (1984 words) Peripheral (64 words)
System (1984 words) Peripheral (64 words)
System (12K words) Data RAM (2K words)
0x0400 0x03FF
0x0800 0x07FF 0x0000
System (13K words)
Data RAM (1K words)
System (12K words)
0x0800 0x07FF
Data RAM (2K words)
0x0C00 0x0BFF
System (11K words) Data RAM (3K words)
Caution
No program or data must be stored to the addresses reserved for the system, nor must these addresses be accessed. If any of these addresses is accessed, normal operation of the PD7701x family is not guaranteed.
Note The PD77019-013 does not have the internal ROM of the PD77019.
PD7701x Family User's Manual
233
Appendix A Device Summary
A.7 Memory Map
[MEMO]
234
PD7701x Family User's Manual
Appendix B
Ordering Information
B.1 Ordering Information
Part Number Package 160-pin plastic QFP (fine pitch) (24 x 24 mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm) 116-pin plastic BGA (fine pitch) (12 x 12 mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm)
1 2 3 4 5 6 A B C
PD77016GM-KMD PD77015GC-xxx-9EU PD77017GC-xxx-9EU PD77018GC-xxx-9EU PD77018AGC-xxx-9EU PD77018AS9-xxx-YJC PD77019GC-xxx-9EU PD77019GC-013-9EU
Remark xxx indicates code suffix.
PD7701x Family User's Manual
235
Appendix B Ordering Information
B.2 Mask Option
B.2 Mask Option
The PD77015, 77017, 77018, 77018A, and 77019 are provided with a PLL and have the following mask option functions.
B.2.1 Disabling CLKOUT output
An internal system clock is generated from an external clock input to the X1 pin to serve as the internal basic timing of the device. This internal system clock is also output from the CLKOUT pin, but this output can be disabled by mask option.
B.2.2 Clock multiple
The external clock is multiplied by the PLL. The multiple can be set by mask option. Available frequency ratios of the external clock to the internal system clock are as follows. However, the multiplication rate of the mask option of the PD77019-013 is fixed to 4 times. * 1 (external): 1 (internal) * 1 (external): 2 (internal) * 1 (external): 3 (internal) (PD77018A and 77019 only) * 1 (external): 4 (internal) * 1 (external): 8 (internal)
B.3 Mask ROM Ordering Format
For how to place your order for a mask ROM, refer to "WB77016 User's Manual".
236
PD7701x Family User's Manual
Appendix C
Index
C.1 Key Words
8-bit parallel port ............................................ 171 16-bit data format ........................................... 139 32-bit data format ........................................... 139 40-bit data format ........................................... 139 Bus arbitration timing ..................................... 122 Bus hold acknowledge output pin .................. 115 Bus hold request input pin ............................. 115 Bus strobe output pin ..................................... 115 Bus strobe signal ........................................... 115 Byte boot ........................................................ 204
1 2 3 4
[C]
Chip select ..................................................... 174 Clock ................................................................ 57 Clock generator ............................................... 57 Crystal .............................................................. 59
[A]
Address ALU .................................................. 124 Address output pin ......................................... 114 Addressing mode ........................................... 124 Architecture ...................................................... 49 Arithmetic logic unit ........................................ 136
5 6 A B C
[B]
Barrel shifter ................................................... 149 Bit manipulation enable bit ............................ 188 Bit manipulation port specification bit ............ 188 Bit reverse access ......................................... 128 Bit reverse operation ...................................... 128 Boot function .................................................. 199 Boot time ........................................................ 212 Boot up ROM ................................................. 200 Break function ................................................ 196 Bus access error flag ..................................... 110 Bus arbitration ................................................ 122
PD7701x Family User's Manual
[D]
Data addressing unit ...................................... 111 Data ALU ....................................................... 147 Data format .................................................... 139 Data I/O pin .................................................... 115 Data memory ................................................. 112 Data memory addressing ............................... 124 Data memory map ................................. 112, 233 Data memory space ....................................... 112 Data memory wait cycle control ..................... 119 Data memory wait cycle register ................... 119
237
Appendix C Index
C.1 Key Words
Data pointer ................................................... 124 Data RAM ...................................................... 113 Data ROM ...................................................... 113 Data wait cycle register .................................. 119 Debug function ............................................... 196 Debug interface ............................................. 195 Debug pin ....................................................... 195 Development tools ......................................... 213 Direct addressing ........................................... 125
[H]
Halt mode ......................................................... 66 Handshake ............................................. 167, 181 Hardware reset ................................................ 61 Hardware tool ................................................. 215 High-speed simulator ..................................... 214 Hold acknowledge ......................................... 115 Hold request ................................................... 115 Host address .................................................. 174 Host boot ........................................................ 203
[E]
Error status register ....................................... 110 External clock................................................... 58 External clock input .......................................... 58 External data memory .................................... 114 External data memory address bus ............... 114 External data memory interface ..................... 114 External data memory read timing ................. 117 External data memory space ......................... 114 External data memory write timing ................ 118 External instruction memory ............................ 73 External instruction memory address bus ....... 74 External instruction memory interface ............. 73 External interface ........................................... 151 External interrupt ............................................. 96 External memory ...................................... 73, 114 External memory wait cycle register ................ 76
Host chip select ............................................. 174 Host data ........................................................ 174 Host data bus ................................................. 171 Host data input register .................................. 172 Host data output register ............................... 172 Host data register .......................................... 176 Host I/O .......................................................... 171 Host interface ................................................. 171 Host interface select signal ............................ 174 Host interface status register ......................... 176 Host read enable ........................................... 174 Host read enable flag ..................................... 177 Host read error flag ........................................ 177 Host read strobe ............................................ 174 Host read timing ............................................. 179 Host write enable ........................................... 174 Host write enable flag .................................... 177 Host write error flag ....................................... 177 Host write strobe ............................................ 174
[F]
Fixed-point data format .................................. 139
Host write timing ............................................ 180
[I] [G]
General-purpose I/O pin ................................ 187 General-purpose I/O port ....................... 185, 187 General-purpose register ............................... 136 I/O mode status bit ......................................... 188 I/O specification bit ........................................ 188 In-circuit emulator .......................................... 215 Index register ................................................. 124 Indirect addressing ........................................ 126 Initialize ............................................................ 61
PD7701x Family User's Manual
238
Appendix C Index
C.1 Key Words
Instruction address output pin ......................... 74 Instruction code I/O pin .................................... 74 Instruction cycle ............................................... 63 Instruction decode ........................................... 63 Instruction fetch ............................................... 63 Instruction memory .......................................... 72 Instruction memory map .......................... 72, 233 Instruction memory space ........................ 72, 233 Instruction memory wait cycle control ............. 77 Instruction memory wait cycle register ............ 76 Instruction memory write strobe output pin ..... 74 Instruction RAM ............................................... 72 Instruction ROM ............................................... 72 Integer data format ........................................ 140 Integrated development environment ............ 214 Internal instruction memory area ..................... 73 Internal instruction RAM .................................. 73 Internal interrupt ............................................... 94 Internal memory ............................................. 113 Internal peripheral .......................................... 151 Internal peripheral area .................................. 151 Internal system clock ....................................... 57 Interrupt ............................................................ 94 Interrupt cause ................................................. 94 Interrupt control function .................................. 95 Interrupt enable flag ......................................... 99 Interrupt enable flag stack register ................ 101 Interrupt request pin ......................................... 94 Interrupt servicing ............................................ 98 Interrupt vector ................................................. 97
Loop stack overflow ......................................... 87 Loop stack pointer ........................................... 87 Loop stack underflow ....................................... 87 Loop start address ........................................... 86 Loop start address register .............................. 86
[M]
Main bus .......................................................... 51 Memory interface ..................................... 79, 114 Memory mapped I/O ...................................... 151 Memory mapped register ............................... 152 Memory read output pin ................................. 115 Memory select signal ..................................... 114 Memory space ......................................... 72, 112 Memory write output pin ................................ 115 Mode setting enable bit .................................. 188 Mode setting port specification bit ................. 188 Modulo operation ........................................... 130 Modulo register .............................................. 124 Multiplexer ...................................................... 124 Multiplication function .................................... 141 Multiply accumulator ...................................... 141
[N]
No-break monitor function ............................. 196 Number of data memory wait cycles ............. 121 Number of instruction memory wait cycles ...... 77
[O] [L]
Logical operation instruction .......................... 148 Loop counter .................................................... 86 Loop end address ............................................ 86 Loop end address register ............................... 86 Loop stack ....................................................... 86 Loop stack error flag ...................................... 110 On-chip emulation function ............................ 196 Op code ........................................................... 63 Operation unit ................................................ 135 Overflow error flag ......................................... 110
PD7701x Family User's Manual
239
Appendix C Index
C.1 Key Words
[P]
Package ......................................................... 235 Peripheral ....................................................... 151 Peripheral bus .................................................. 56 Peripheral unit ................................................ 151 Pin configurations ............................................ 26 Pin functions .................................................... 25 Pin organizations ............................................. 32 Pipeline ............................................................ 63 Pipeline processing .......................................... 63 Pointer register .............................................. 124 Port command register .................................. 187 Port data register ........................................... 187 Port set/reset specification bit ........................ 188 Program control unit ........................................ 71 Program counter .............................................. 72 Program memory ............................................. 72 Program memory write strobe ......................... 74
Serial input continuous mode setting flag ...... 160 Serial input enable ......................................... 157 Serial input shift register ........................ 154, 159 Serial input timing .......................................... 164 Serial input transfer format setting bit ............ 160 Serial input word length setting bit................. 160 Serial interface ............................................... 153 Serial output enable ....................................... 157 Serial output request .............................. 154, 156 Serial output shift register ...................... 154, 159 Serial output timing ........................................ 162 Serial output transfer format setting bit ......... 160 Serial output word length setting bit .............. 160 Serial status register ...................................... 158 Shift operation instruction .............................. 149 Shift register ................................................... 159 Single serial input enable flag ........................ 160 Single serial input mode ................................ 161 Software loop stack ......................................... 86 Software simulator ......................................... 214
[R]
Read strobe output pin .................................. 115 Reboot ................................................... 201, 210 Register list .................................................... 217 Repeat counter ................................................ 86 Reserved bit ................................................... 188 Ring count ...................................................... 132
Software tool .................................................. 213 Stack ................................................................ 80 Stack error flag .............................................. 110 Stack overflow .................................................. 80 Stack pointer .................................................... 80 Stack underflow ............................................... 80 Standby function .............................................. 66 Status register .................................................. 99 Status transition mode ................................... 161
[S]
Self boot ......................................................... 201 Serial clock ..................................................... 156 Serial data input ............................................. 157 Serial data input register ........................ 154, 158 Serial data output ........................................... 157 Serial data output register ..................... 154, 158 Serial data register ......................................... 158 Serial I/O ........................................................ 153 Serial input acknowledge ....................... 154, 157
Stop mode ........................................................ 69 System clock .................................................... 57 System control unit .......................................... 57 System software ............................................ 214 System software for in-circuit emulator ......... 214
[T]
Trinomial operation ........................................ 143
240
PD7701x Family User's Manual
Appendix C Index
C.1 Key Words
[W]
Wait controller ........................................ 119, 194 Wait cycle ................................................. 77, 121 Wait cycle control ................................... 168, 182 Wait cycle register ................................... 76, 120 Wait input pin ................................................. 115 Wait signal ....................................................... 36 Word boot ...................................................... 204 Write strobe output pin ................................... 115
PD7701x Family User's Manual
241
Appendix C Index
C.2 Acronyms, etc.
C.2 Acronyms, etc.
[A]
ALU ................................................................ 147
[G]
GND ........................................................... 35, 41
[H]
HA0 ................................................................ 174 HA1 ................................................................ 174
[B]
B0, B1 ............................................................ 188 bac ................................................................. 110 BE .................................................................. 188 BSFT .............................................................. 149 BSTB .............................................................. 115
HAWE ............................................................ 177 HCS ................................................................ 174 HCTL .............................................................. 171 HD0 - HD7 ..................................................... 174 HDT ................................................................ 176 HLER ............................................................. 177 HOLDAK ........................................................ 115 HOLDRQ ........................................................ 115
[C]
C compiler ...................................................... 214 CLKIN .............................................................. 57 CLKOUT .......................................................... 57
HRD ............................................................... 174 HRE ................................................................ 174 HREF ............................................................. 177 HREM ............................................................ 177 HRER ............................................................. 177 HSER ............................................................. 177
[D]
D0 - D15 ......................................................... 115 DA0 - DA15 .................................................... 114 DMX ............................................................... 124 DMY ............................................................... 124 DN0 - DN7 ..................................................... 124 DP0 - DP7 ...................................................... 124 DWTR ............................................................ 119
HST ................................................................ 176 HWE ............................................................... 174 HWEF ............................................................ 177 HWEM ............................................................ 177 HWER ............................................................ 177 HWR............................................................... 174
[I]
I.C. ................................................................... 25 IA0 - IA15 ......................................................... 74
[E]
EB .................................................................... 99 EB-77017 ....................................................... 216 EI ...................................................................... 99 EIR ................................................................. 101 EP .................................................................... 99 ESR ................................................................ 110
ID0 - ID31 ......................................................... 74 ID77016 ......................................................... 214 IE-77016-CM-EM6 ......................................... 215 IE-77016-PC .................................................. 215 INT1 - INT4 ...................................................... 96 INTC ................................................................. 71 IO ................................................................... 188 IWTR ................................................................ 76
242
PD7701x Family User's Manual
Appendix C Index
C.2 Acronyms, etc.
[L]
LC ..................................................................... 86 LEA .................................................................. 86 LF ................................................................... 100 LRC .................................................................. 88 LSA .................................................................. 86 lse .................................................................. 110 LSP .................................................................. 87 LSTK ................................................................ 86
[R]
R0 - R7 ........................................................... 136 RC .................................................................... 86 RESET ............................................................. 61
[S]
SCK1, SCK2 .................................................. 156 SCTL .............................................................. 153 SDT1, SDT2 ................................................... 158 SI1, SI2 .......................................................... 157
[M]
M0 - M3 .......................................................... 188 MAC ............................................................... 141 MAC input shifter ........................................... 141 ME .................................................................. 188 MRD ............................................................... 115 MSFT ............................................................. 141 MUX ............................................................... 124 MWR .............................................................. 115
SIAK1, SIAK2 ................................................. 157 SIBL ............................................................... 160 SICM .............................................................. 160 SIEF ............................................................... 160 SIEN1, SIEN2 ................................................ 157 SIS1, SIS2 ..................................................... 159 SITF ............................................................... 160 SLEF .............................................................. 160 SLER .............................................................. 160 SLWE ............................................................. 160 SM77016 ........................................................ 214
[N]
NC .................................................................... 25
SM77016-H .................................................... 214 SO1, SO2 ....................................................... 157 SOBL ............................................................. 160
[O]
ovf .................................................................. 110
SOEN1, SOEN2 ............................................. 157 SORQ1, SORQ2 .................................... 154, 156 SOS1, SOS2 .......................................... 154, 159 SOTF ............................................................. 160
[P]
P0 - P3 ........................................................... 187 PC .................................................................... 72 PC stack ........................................................... 80 PCD................................................................ 187 PDT ................................................................ 187 Power Supply ................................................... 25 PSR ................................................................ 188 PWR ................................................................. 74
SP .................................................................... 80 SR .................................................................... 99 SSEF .............................................................. 160 SSER ............................................................. 160 SST ................................................................ 158 SST1, SST2 ................................................... 158 SSWE ............................................................ 160 ste .................................................................. 110 STK .................................................................. 80
PD7701x Family User's Manual
243
Appendix C Index
C.2 Acronyms, etc.
[T]
TCK ................................................................ 195 TDI ................................................................. 195 TDO ................................................................ 195 TGC-100SDW ................................................ 215 TICE ............................................................... 195 TMS ................................................................ 195
Y memory ....................................................... 112 Y memory boot ............................................... 206 Y memory space ............................................ 112 YAA ........................................................ 111, 124 YBRC ..................................................... 111, 124
[U]
UF0, UF1 ....................................................... 177
[V]
VDD ............................................................................ 35, 41
[W]
WAIT .............................................................. 115 WB77016 ....................................................... 214 WCTL ............................................................. 194 Windows-based development environment ... 213
[X]
X data bus ........................................................ 54 X memory ....................................................... 112 X memory boot ............................................... 206 X memory space ............................................ 112 X/Y ................................................................. 114 X1 ..................................................................... 59 X2 ..................................................................... 59 XAA ........................................................ 111, 124 XBRC ..................................................... 111, 124
[Y]
Y data bus ........................................................ 55
244
PD7701x Family User's Manual
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